Ricoh Company, Ltd.

Katsuhiko Manabe

Makoto Matsushima

Hiroki Fukuoka

Tomonari Katoh

Minoru Sugiyama

Tadayoshi Ueda

Noriaki Hatanaka

A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

DC converter with halt mode setting means

A method and apparatus of detecting a connection status of a digital video apparatus to a peripheral apparatus includes a digital video encoder configured to receive a digital video signal, and convert and output the digital video signal into an analog video signal, and a determination circuit configured to detect a voltage level of a horizontal synchronization signal of the analog video signal in a vertical blanking time determined by vertical synchronization signals, and determine whether the digital video apparatus is connected to a peripheral apparatus based on a detection result of the voltage of the horizontal synchronization signal of the analog video signal.

Digital video apparatus capable of detecting its status of connection to peripheral apparatus

An amplifying circuit includes a battery power source, a regulator that regulates an output of the battery power source and generates a reference voltage, and a signal ground generating device that generates and outputs a signal ground by changing the reference voltage in accordance with deterioration detected from the battery power source. An operational amplifier is provided to amplify and output a signal having prescribed waveform to be input to a speaker. The operational amplifier uses a battery power source as a driving power source of its own. The signal ground is positioned at a center of vibration amplitude of the waveform.

Amplifying circuit, speaker system, and mobile information terminal employing amplifying circuit

In an electronic still camera, image data obtained by a camera image pickup section are transmitted to an image data compression/extension circuit and are coded by this circuit. The coded image data are recorded to a FIFO circuit. The image data are then DMA-transferred to a memory card by a DMA controller within a memory card interface (I/F) and are recorded to the memory card. When the image data are regenerated, the image data are DMA-transferred in a reverse direction. In another camera, image data are outputted from a charge coupled device (CCD) and are converted to a digital signal. Sound data are outputted from a microphone and are converted to a digital signal. File header information is constructed by the image and sound data and is stored to a RAM of a memory card interface in advance. The file header information is recorded to a memory card by a direct memory access (DMA) control section. In another camera, a central processing unit (CPU) selects an image or sound format recorded to a recording medium. When these formats are used in various kinds of application programs in an information equipment, data are recorded to the recording medium in accordance with these formats.

Electronic still camera

An electronic still camera which photographs an object and outputs image data. An image data coding device codes the image data. The coded image data is recorded to a recording medium. Sound data can also be converted to an electric signal and the sound data can be coded, converted to an electric signal, and then recorded to the recording media. A rearrangeable unused region of the recording media can be used as a work area for a file control work.

In an electronic still camera, image data obtained by a camera image pickup section are transmitted to an image data compression/extension circuit and are coded by this circuit. The coded image data are recorded to a FIFO circuit. The image data are then DMA-transferred to a memory card by a DMA controller within a memory card interface (I/F) and are recorded to the memory card. When the image data are regenerated, the image data are DMA-transferred in a reverse direction. In another camera, image data are outputted from a charge coupled device (CCD) and are converted to a digital signal. Sound data are outputted from a microphone and are converted to a digital signal. File header information is constructed by the image and sound data and is stored to a RAM of a memory card interface in advance. The file header information is recorded to a memory card by a direct memory access (DMA) control section.

In an electronic still camera, image data obtained by a camera image pickup section are transmitted to an image data compression/extension circuit and are coded by this circuit. The coded image data are recorded to a FIFO circuit. The image data are then DMA-transferred to a memory card by a DMA controller within a memory card interface (I/F) and are recorded to the memory card. When the image data are regenerated, the image data are DMA-transferred in a reverse direction.

A digital still video camera including a camera processor which processes image data of a subject, a recording processor which generates recording data based on the processed image data, a recording controller which controls recording of the recording data to a recording medium, a memory which stores image data processed by the camera processor and recording data recorded in the recording medium, a control device which controls the camera processor, the recording processor, and the recording controller, and an evacuating/writing device which interrupts control by the control device and evacuates/writes the recorded recording data between the recording medium and the memory.

Digital still video camera

A data writing operation of a memory card is performed from a first EEPROM chip. Writing commands are given every time data in a memory block unit are completely transferred. Each of four EEPROM chips is performing the writing operation when data of the four EEPROM chips are completely written to the memory card. A systematic side waits for the next data transfer in view of an RDY/BSY signal of the memory card. The data writing operation from the systematic side to each of the four EEPROM chips is sequentially changed by monitoring an RDY/BSY1 signal of the first EEPROM chip. In this construction of the memory card, data can be preferably written and read from the memory card at a high speed.

Memory card having a plurality of EEPROM chips

A converting circuit has a memory of a capacity of at least n.times.b.sub.max pixels when b.sub.max is set to the number of valid pixels in a frequency mode providing a largest number of valid pixels for one horizontal period with respect to a plurality of frequency modes. A memory controller has a read only memory (ROM) table for storing an address generating order in advance in the frequency mode of the number b.sub.max of valid pixels. In the memory controller, an address is generated in accordance with address generating order stored in the ROM table when line data in another frequency mode are stored in the memory. Data of n.times.b valid pixels are stored in the memory every n horizontal periods when the number of valid pixels for one horizontal period in the other frequency mode is set to b. In the memory controller, data of invalid pixels are store in the memory at the remaining n.times.b.sub.max -n.times.b addresses. A data mask inhibits data of (b.sub.max /n)-(b/n) invalid pixel blocks every n horizontal periods with respect to block data read and converted at a reading time from being outputted to the next stage.

Line data-block data converting circuit

A digital teleconverter includes a component signal generation circuit, an encoder for obtaining a composite signal from the component signal, an image processing unit and a selector for selecting an image processing mode. The component signal generation circuit generates component signals comprising a luminance signal and color difference signals in response to an object image transmitted from an image pickup element. The encoder converts the component signals transmitted from the component signal generation circuit to a composite signal. The image processing unit performs a digital image processing on the basis of either the component signals or the composite signal. The selector selects either a video signal processed by and transmitted from the image processing unit or an original video signal of the object image.

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Hyogo-ken, Japan

Katsuhiko Manabe