Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Nuvoton Technology Corporation Japan

Panasonic Intellectual Property Management Co., Ltd.

Katsuhiko Kawashima

Masahiro Maeda

Masatoshi Kamitani

Yusuke Kanda

Tsuyoshi Tanaka

Yoshiharu Anda

Kazuki Tateoka

Shingo Matsuda

Mitsuru Nishitsuji

Akihiko Nishio

Yorito Ota

Tadayoshi Nakatsuka

Yoshinori Takami

Takashi Yui

Hiroyuki Masato

Keiichi Murayama

Junko Iwanaga

Hiroshi Sugiyama

Kenichi Miyajima

Hirokazu Makihara

Hirotaka Miyamoto

Masato Seki

Hiroaki Kawano

Dai Motojima

Wataru Kanaga

A power amplifier semiconductor device includes: a substrate; a semiconductor layer provided on the surface of the substrate and including a plurality of unit HEMTs; a connection layer provided on the semiconductor layer and including a source electrode, a drain electrode, and a gate electrode of each of the plurality of unit HEMTs; a terminal layer provided on the connection layer; a back electrode which is provided on the bottom surface of the substrate and whose potential is set to a source potential; and substrate vias that pass through the substrate and have a shield wiring layer on inner walls of the substrate vias. In plan view, either one of the drain aggregation portion or the gate aggregation portion is or both of the drain aggregation portion and the gate aggregation portion are each surrounded by the substrate vias.

Power amplifier semiconductor device

A semiconductor device includes: a gate electrode including a junction portion forming a Schottky junction with a barrier layer; a projecting portion including first and second gate field plates and projecting from the junction portion; and an insulating layer including first and second sidewalls. An angle formed between a highest position of a bottom surface of the first gate field plate and a main surface of a substrate, viewed from the first position, is a second elevation angle. An angle formed between an end on the drain electrode side of a lowest portion of a bottom surface of the second gate field plate and the main surface, viewed from the first position, is a third elevation angle. The second elevation angle is larger than the third elevation angle. The bottom surface of the second gate field plate includes an inclined surface where a distance from the barrier layer monotonically increases.

Semiconductor device

A semiconductor device for power amplification includes: a source electrode, a drain electrode, and a gate electrode disposed above a semiconductor stack structure including a first nitride semiconductor layer and a second nitride semiconductor layer; and a source field plate that is disposed above the semiconductor stack structure between the gate electrode and the drain electrode, and has a same potential as a potential of the source electrode. The source field plate has a staircase shape, and even when length LF2 of an upper section is increased for electric field relaxation, an increase in parasitic capacitance Cds generated between the source field plate and a 2DEG surface is inhibited.

Semiconductor device for power amplification

A semiconductor device includes a source electrode portion and a drain electrode formed on a semiconductor stacked body so as to be at an interval from each other, and a gate electrode formed between the source electrode portion and the drain electrode at an interval from the source electrode portion and the drain electrode. The source electrode portion includes a first recess electrode being directly in contact with a two-dimensional electron gas layer formed in the first nitride semiconductor layer, and a surface electrode formed between the gate electrode and the first recess electrode and connected conductively to the two-dimensional electron gas layer. A source potential is applied to the surface electrode and the recess electrode, and a width of the surface electrode in a gate-source direction is 0.4 times or more a distance between a gate-side end of the surface electrode and a source-side end of the gate electrode.

A high-frequency power amplifier that amplifies a high-frequency input signal and outputs a signal having one power selected from a plurality of powers includes a high output route that is a circuit, which amplifies the input signal and outputs a signal of a high power, and a medium output route that is a circuit, which amplifies the input signal and outputs a signal of a medium power. The high output route includes a high-output amplifier that amplifies the input signal, an output matching circuit that is connected to an output node of the high-output amplifier, and a switch element that is connected to an output node of the output matching circuit. The medium output route includes a medium-output amplifier that amplifies the input signal and a switch element that is connected between an output node of the medium-output amplifier and an output node of the output matching circuit.

High-frequency power amplifier

The radio frequency power amplifier is connected between an other end of the first switching element and an other end of the second switching element, supplies power to a second amplifier via the first switching element and a second matching circuit, and includes a first power supply line for supplying power to the third amplifier via a second switching element and a third matching circuit, and the other end of the first switching element is connected to an input node of the first matching circuit, the other end of the second switching element is connected to the input node of the first matching circuit via the first power supply line, and an impedance of an output side of the RF power amplifier as viewed from an output node of the third amplifier is higher than an impedance of the RF power amplifier as viewed from an output node of the second amplifier.

Radio frequency power amplifier

A base mesa finger (an emitter ledge layer, a base layer, and a collector layer) is interposed between two collector fingers (collector electrodes), and on the base mesa finger, a base finger (a base electrode) and two emitter fingers (an emitter layerand an emitter electrode) on both sides of the base finger, are formed. The two emitter fingers are formed symmetric with respect to the base finger as a reference.

Bipolar transistor and power amplifier

A power amplifier amplifies an input signal having a fundamental frequency of which band width ranges between a first fundamental frequency Fand a second fundamental frequency F. The power amplifier includes a power amplifier transistor for amplifying the input signal and an output matching circuit for suppressing a harmonic component included in an output signal from the power amplifier transistor. The output matching circuit includes: a first second-order harmonic series resonant circuit including a first inductor and a first capacitor and having a frequency twice as large as Fas a resonance frequency; and a second second-order harmonic series resonant circuit including a second inductor and a second capacitor and having a frequency twice as large as Fas a resonance frequency.

Power amplifier

A high-frequency power amplifier device including: a power amplifier circuit which amplifies a high-frequency signal; an output matching circuit connected to an output side of the power amplifier circuit; and a high-frequency circuit connected to an output side of the output matching circuit, which is designed so that X[f] satisfies the relationship expressed as X[L]&#x3c;X[H], where j denotes an imaginary number, f denotes a frequency, an impedance of the high-frequency circuit viewed from the output matching circuit is defined as Z[f]=R[f]+jX[f], L denotes a lower limit of the frequency, and H denotes an upper limit of the frequency.

High-frequency power amplifier device

A capacitoris formed by laminating a lower electrode, a dielectricand an upper electrodein this order. An inductoris formed as a thin metal wiring of a spiral shape so as to have an inductor component. The inductoris formed in the same wiring layer and of the same metal material as the lower electrodeof the capacitorconnected to a base electrodeof a transistor. The DC bias is inputted to the base B of the transistorthrough the inductorof a spiral shape from the DC bias supply wiring BP, and a radio frequency signal is inputted to the base B of the transistorthrough the capacitor

Semiconductor integrated circuit apparatus

The transistor circuitincludes a plurality of transistor cellseach having a transistor, a base ballast resistor, a capacitor, and an inductor. The transistorshave the respective collectors commonly connected to a collector terminalof the transistor circuitand the respective emitters commonly connected to an emitter terminalthereof. Each base ballast resistoris connected to bases of the transistorat one end and to a base terminalof the transistor circuitat the other end. The capacitoris serially connected to the inductor, thus to form a serial resonant circuit, which is connected in parallel with the base ballast resistorand provided between the bases of the transistorand the base terminalof the transistor circuitand connected thereto.

Transistor circuit

An organic polymer film patterning method includes the steps of: defining a resist film on a selected area of a substrate; depositing an organic polymer film over the substrate by a plasma CVD process so that the resist film is covered with part of the organic polymer film; and removing the resist film along with the part of the organic polymer film that has covered the resist film.

Method of patterning organic polymer film and method for fabricating semiconductor device

First, an insulating film is formed over the entire surface of a semiconductor substrate including a channel region for a field effect transistor. The insulating film has a gate electrode opening over the channel region. Next, a protective film is deposited over the entire surface of the insulating film. Then, a lower electrode, a capacitive insulating film and an upper electrode are formed in this order in a region on the protective film where a capacitor will be formed. Subsequently, part of the protective film, with which the gate electrode opening of the insulating film has been filled in, is removed, thereby exposing the semiconductor substrate within the gate electrode opening. And then a gate electrode is formed to fill in the gate electrode opening again.

Method for fabricating semiconductor integrated circuit device

A conductive layer made of n-type GaAs is formed on a semi-insulating substrate made of GaAs. A pair of contact regions made of n.sup.+ -type GaAs are formed on the conductive layer. A source electrode is formed on the left-hand contact region, while a drain electrode is formed on the right-hand contact region. A gate recessed region is formed in the region of the conductive layer located between the pair of contact regions so that a gate electrode is formed on the gate recessed region. A depressed portion is formed in the gate recessed region of the conductive layer. The wall face of the depressed portion closer to the gate electrode is flush with or protruding from the side face of the gate electrode facing the drain electrode.

Growing community of inventors

Hyogo, Japan

Katsuhiko Kawashima