Fujitsu Corporation

Katsuhiko Kabashima

Yoshihiro Takemae

Shigeki Nozaki

Seiji Enomoto

Tsutomu Mezawa

Tomio Nakano

Masao Nakano

Kiyoshi Miyasaka

Tsuyoshi Ohira

Takeo Tatematsu

Hatsuo Miyahara

Masakazu Kanai

A semiconductor device, provided with a buffer, which comprises a first transistor for pulling up the output terminal voltage, a second transistor for pulling down the output terminal voltage, and a charge-pumping circuit for maintaining the output terminal voltage at a level higher than the power source voltage by charge pumping when the output terminal voltage is at a high level. The semiconductor device further comprises a circuit for pulling down the output terminal voltage during the period from when power is supplied to when an input signal is supplied to the buffer.

Semiconductor device for pulling down output terminal voltage

A dynamic semiconductor memory device having a refresh-address generator, includes an initial resetting circuit for resetting the output signals of a refresh-address counter when the power supply is turned on, thereby eliminating the need for counter checking procedures prior to the examination of the refresh-address generator.

Dynamic semiconductor memory device

A semiconductor integrated circuit (IC) device includes therein a test circuit. The test circuit operates to distinguish the power source level during the testing or ground level occurring at an internal node located inside the semiconductor chip. The test circuit includes a series-connected MIS transistor and an MIS diode. The gate of the MIS transistor is connected to the internal node. The MIS diode is connected to an external input/output (I/O) pin. The level at the internal node, i.e., the power source level or the ground level, can be distinguished by a first voltage level or a second voltage level applied to the external I/O pin, whichever enables a current to be drawn from the external I/O pin.

Semiconductor integrated circuit device

A semiconductor circuit for driving a clock signal line comprising a first circuit for pulling up the potential of the clock signal line to the source voltage and a second circuit for pulling down the potential of the clock signal line to a lower voltage. A capacitor is connected to the clock signal line for receiving a potential push signal and pushing the potential of the clock signal line higher than the source voltage. The capacitor performs the function of capacitance only after the potential of the clock signal line is raised to the source voltage. The operational speed of a dynamic memory device associated with the semiconductor device is then enhanced.

Semiconductor circuit for enabling a quick rise of the potential _on the

In a semiconductor device having a signal line on which a voltage higher than the voltage supply is generated, a conductive layer following the potential variance of the voltage supply is positioned under an insulating film directly below the signal line in order to make the level of the signal line follow the potential variance of the voltage supply.

Semiconductor device having a circuit for generating a voltage higher

A buffer circuit comprises a flip-flop which is receives an external input via a first input circuit and a reference voltage via a second input circuit. Internal complementary outputs are then produced via an output circuit. The flip-flop cooperates with at least one level setting device by way of a second input circuit. The level setting device functions to produce a voltage level to deactivate the second input circuit during activation of the flip-flop.

Buffer circuit

An address buffer for a dynamic memory includes a flip-flop. The flip-flop is coupled at its one input/output terminal with both a first input circuit and a third input circuit connected in parallel with each other and at its other input/output terminal with a second input circuit. The second input circuit receives a reference voltage and is activated by an external address timing clock during a normal operation mode. The first input circuit is also activated by the external address timing clock, but receives an external address. The third input circuit receives an internal refresh address and is activated by an internal refresh address. The address buffer cooperates with a switcher which produces the internal refresh address timing clock and the external address timing clock, alternatively, by switching a basic timing clock generated by an address drive clock generator.

Address Buffer

A semiconductor circuit used as a buffer circuit having an input stage circuit for receiving an input clock signal and an inverted input clock signal, a bootstrap circuit including a transistor for receiving the output of the input stage circuit and for maintaining the gate voltage of the transistor at a high level during the standby period, and an output circuit, including a transistor which is switched on and off by the output of the bootstrap circuit, for generating an output clock signal; the semiconductor circuit further comprising a current leak circuit for maintaining, during the standby period, the voltage of a point in the semiconductor circuit which is charged during the standby period at the value corresponding to the voltage of the power source, whereby the delay of the output clock signal, caused of the fluctuation by the voltage of the power supply during the standby period, is improved and then the high speed access time in the dynamic memory is carried out.

Buffer circuit including a current leak circuit for maintaining the

An active pull-up circuit for use in a sense amplifier or the like, comprises an enhancement type MIS transistor, a MIS capacitor controlled by a clock signal, and a depletion type MIS transistor controlled by another clock signal (.phi..sub.2 '). In this circuit, the two clock signals are bilevel signals having potentials which are the same as potentials of two power supplies.

Active pull-up circuit

A reset circuit used for resetting, for example a memory device after a reading-out from a memory is effected, comprises fist and second reset transistors, for connecting first and second circuits to a common voltage source, and a short-circuit transistor, having a lower threshold voltage than the threshold voltage of said first and second reset transistors, for connecting said first and second circuits when said short circuit transistor receives the same input signal as supplied to said first and second reset transistors.

Reset circuit

A semiconductor memory device having flip-flop circuits, in which first and second bit lines are connected to each of the flip-flop circuits as a sense amplifier, the potential of the second bit line being opposite to the potential of the first bit line, and the first and second data bus lines cross perpendicularly to the first and second bit lines, respectively, the first and second dummy lines are arranged in parallel with the first and second data bus lines respectively, in order to prevent erroneous operation of an I/O amplifier connected to the first and second data bus lines.

Semiconductor memory device having flip-flop circuits

An integrated semiconductor memory device is formed on a semiconductor substrate of one conductivity type on which there are provided peripheral circuits consisting of a pluality of memory cells each containing a storage capacitor and an IG FET. The IG FET in each memory cell acts as a transfer gate which is disposed on a surface region having the same conductivity type as that of the substrate and higher impurity concentrations than that of the substrate. The transfer gate has a gate threshold value which is higher than that of the IG FET in the peripheral circuits and which is insensitive to a noise pulse supplied thereto, whereby the destruction of data by noise pulse can be effectively prevented.

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Kawasaki, Japan

Katsuhiko Kabashima