Toshiba Memory Corporation

Kioxia Corporation

Katsuhiko Iwai

Shinji Maeda

Takashi Ogasawara

Takaaki Ikeda

Shigeo Kurakata

Takuzo Watanabe

A memory system includes a nonvolatile memory and a control circuit. The nonvolatile memory includes a plurality of word lines, a plurality of bit lines, and a plurality of storage elements. The control circuit includes an ECC circuit that detects and corrects a data error stored in the plurality of storage elements, acquires first data by reading data stored in the plurality of storage elements of a page connected to the same word line with a first read voltage, acquires second data obtained by correcting the first data when the first data can be corrected by the ECC circuit, and writes data based on the second data to the plurality of storage elements of the page.

Memory system and nonvolatile memory for improving reliability of stored data and shortening operation time

A memory system comprises a nonvolatile memory including a plurality of blocks, a memory controller capable of controlling the nonvolatile memory, and a tag information management table in which tag information allocated to an address of data written to a block of nonvolatile memory, is stored, wherein the tag information is representative of the number of erasures of the block. The memory controller performs garbage collection of the nonvolatile memory based on the tag information.

Memory system

A semiconductor device includes a transmission and reception circuit and a control circuit. The transmission and reception circuit transmits and receives a signal to and from a semiconductor memory device. The control circuit acquires threshold voltage distribution information of a memory element connected to a word line for read disturb detection to which a second voltage higher than a first voltage applied to an adjacent word line adjacent to a read target word line during a read operation is applied and determines an influence of read disturb based on the threshold voltage distribution information.

Semiconductor device, memory system and semiconductor memory device

A memory apparatus of an embodiment includes a nonvolatile semiconductor memory device, an error correction circuit, a memory circuit, a data distribution circuit, and a processing circuit. The error correction circuit performs error detection in data read from the nonvolatile semiconductor memory device on a processing unit size basis and performs error correction on the data in response to its necessity. The memory circuit stores data on the processing unit size basis. The data distribution circuit transfers the data read from the nonvolatile semiconductor memory device to the error detection circuit and the memory circuit on the processing unit size basis. The processing circuit reads the data from the memory circuit and processes the data in response to the error correction circuit detecting an uncorrectable error in the data.

Memory apparatus and data read method

A memory controller includes a memory interface that is connected to a non-volatile memory that includes a plurality of memory cells, and a control unit. The control unit controls the memory interface to perform writing of data that has a first number of bits to a first memory cell in an n-bit write mode (where n is 2 or more), and when performing reading of the data written into the first memory cell, to control the memory interface to perform reading of data in an m-bit read mode (where m is less than n), as a result of which data that has a second number of bits which is smaller than the first number of bits, is returned from the first memory cell.

Memory controller, memory system, and control method

According to one embodiment, a memory system includes a semiconductor memory including a memory cell, and a controller configured to control the semiconductor memory and capable of creating second data based on first data read from the memory cell. Upon receiving a physical erase request for the first data held in the memory cell from an external device, the controller transmits one of an erase instruction and a write instruction for the second data to the semiconductor memory.

Growing community of inventors

Yokohama, Japan

Katsuhiko Iwai