Renesas Technology Corp.

Renesas Electronics Corporation

Hitachi-high-technologies Corporation

Hitachi, Ltd.

Hitachi Tokyo Electronics Co., Ltd.

Katsuhiko Ichinose

Yusuke Nonaka

Akihiro Shimizu

Nagatoshi Ooki

Fumio Ootsuka

Tomohiro Saito

Shinichiro Mitani

Yutaka Tandai

Tsunehiro Sakai

Tamao Ishikawa

Youhei Yanagida

Shuji Ikeda

Hideo Miura

Yuji Takagi

Hiroyuki Ohta

Takehiro Hirai

Toshifumi Takeda

Tsuyoshi Fujiwara

Takahiro Onai

Hidenori Sato

Yuichi Hamamura

Seiji Isogai

Yukihiro Kumagai

Tomohiro Funakoshi

Naohumi Ohashi

Kazuhisa Hasumi

Masahiro Ushiyama

Koichi Hayakawa

Kazunori Nemoto

Tetsuo Saito

Shoji Wakahara

Tomoko Jinbo

Yukino Ishii

Shigeki Kurihara

A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.

P-channel transistor having an increased channel mobility due to a compressive stress-inducing gate electrode

Semiconductor device and a method of manufacturing the same

A defect image processing apparatus uses a normalized cross correlation to image-match a layout image () acquired from a design data with an image acquired by removing, from a defect image (), the defect area portions thereof, and displays, as a result of that matching, a layout image and defect image () on the display device. In the displayed layout image & defect image (), not only the layout image, the layer of which is the same as that of the defect image (), but also a layout image of another layer is displayed superimposed on the defect image (). This makes it easier to analyze the factor of a systematic defect having occurred due to a positional relationship with another layer.

Defect image processing apparatus, defect image processing method, semiconductor defect classifying apparatus, and semiconductor defect classifying method

Semiconductor device including a film for applying stress to a channel formation region to increase current flow

A defect is efficiently and effectively classified by accurately determining the state of overlap between a design layout pattern and the defect. This leads to simple identification of a systematic defect. A defective image obtained through defect inspection or review of a semiconductor device is automatically pattern-matched with design layout data. A defect is superimposed on a design layout pattern for at least one layer of a target layer, a layer immediately above the target layer, and a layer immediately below the target layer. The state of overlap of the defect is determined as within the pattern, over the pattern, or outside the pattern, and the defect is automatically classified.

Semiconductor defect classifying method, semiconductor defect classifying apparatus, and semiconductor defect classifying program

Semiconductor device including a nitride containing film to generate stress for improving current driving capacity of a field effect transistor

A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.

Structure and method of applying localized stresses to the channels of PFET and NFET transistors for improved performance

CMOS transistors using gate electrodes to increase channel mobilities by inducing localized channel stress

In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride filmfor self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400&#xb0; C. or greater by plasma CVD using a raw material gas including monosilane and nitrogen. A silicon nitride filmconstituting a passivation film is formed at a substrate temperature of about 350&#xb0; C. by plasma CVD using a raw material gas including monosilane, ammonia and nitrogen. The hydrogen content contained in the silicon nitride filmis smaller than that contained in the silicon nitride film, making it possible to suppress hydrogen release from the silicon nitride film

Semiconductor integrated circuit device and process for manufacturing the same

Semiconductor device including stress inducing films formed over n-channel and p-channel field effect transistors and a method of manufacturing the same

The present invention provides a semiconductor device including n-channel field effect transistors and p-channel field effect transistors all of which have excellent drain current characteristics. In a semiconductor device including an n-channel field effect transistorand a p-channel field effect transistor, a stress control filmcovering a gate electrodeof the n-channel field effect transistorundergoes film stress mainly composed of tensile stress. A stress control filmcovering a gate electrodeof the p-channel field effect transistorundergoes film stress mainly caused by compression stress compared to the filmof the n-channel field effect transistor. Accordingly, drain current is expected to be improved in both the n-channel field effect transistor and the p-channel field effect transistor. Consequently, the characteristics can be generally improved.

Semiconductor device with CMOS-field-effect transistors having improved drain current characteristics

An impurity ion of a polarity opposite to that of an impurity ion forming an n-type diffusion layer is implanted into a lower portion of the n-type diffusion region in a region, in which n-channel type MISFET is to be formed, vertically with respect to a main surface of a semiconductor to form a first p-type pocket layer. Subsequently, an impurity of a p conduction type is implanted into a region between the n-type diffusion region and the first p-type pocket layer obliquely relative to the main surface of the semiconductor substrate to form a second p-type pocket layer. In this arrangement, the concentration of the impurity ion forming the second p-type pocket layer is made higher than the concentration of the impurity ion used to form the first p-type pocket layer.

Semiconductor integrated circuit device and method of manufacturing the same

A CVD device () used for depositing a silicon nitride has a structure in which a hot wall furnace () for thermally degrading a source gas and a chamber () for forming a film over a surface of a wafer () are separated from each other. The hot wall furnace () for thermally degrading the source gas is provided above the chamber (), and a heater () capable of setting the inside of the furnace at a high temperature atmosphere of approximately 1200&#xb0; C. is provided at the outer periphery thereof. The source gas, supplied to the hot wall furnace () through pipes () and (), is thermally degraded in this furnace in advance, and degraded components thereof are supplied on a stage () of the chamber () to form a film on the surface of the wafer ().

Method of manufacturing a semiconductor integrated circuit device

A semiconductor integrated circuit device is formed by a semiconductor substrate having an SiGe layer and a first Si layer epitaxially grown thereover, and on which there are element formation regions each partitioned by element isolation regions; a shallow groove isolation, which has a groove formed in each of the element isolation regions and an insulating film inside of the groove, said groove penetrating through the first Si layer and having a bottom in the SiGe layer; a second Si layer formed between the shallow groove isolation and the SiGe layer; and a semiconductor element formed over the main surface of the semiconductor substrate in the element formation regions. This construction enables a reduction in leakage current via the walls of the shallow groove isolation of the strained substrate, thereby improving the element isolation properties.

Semiconductor integrated circuit device

With a gate electrode and side wall spacers being used as masks, ions of an n-type impurity are implanted from the normal line direction of a substrate, whereby source/drain diffused regions are formed. Then, ions of an n-type impurity are introduced by oblique implantation having a predetermined angle relative to the normal line direction of the substrate to form an n-type semiconductor region having an impurity concentration higher than source/drain extended regions. By this method, the junction depth of the semiconductor region becomes smaller than that of the source/drain diffused regions and greater than that of the source/drain extended regions.

Semiconductor integrated circuit device and a method of manufacturing the same

Growing community of inventors

Tokorozawa, Japan

Katsuhiko Ichinose