Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Katsuaki Takagi

Norio Nakagawa

Yoshimune Hagiwara

Hirokazu Aoki

Yuzo Kita

Kazuyoshi Ogawa

Masashi Horiguchi

Masakazu Aoki

Hideo Nakamura

Yuji Yatsuda

Osamu Minato

Tsuneo Funabashi

Tetsuro Honmura

Hideo Hara

Toshiro Tsukada

Shunpei Kawasaki

Nobutaka Amano

Shuichi Torii

Michio Hara

Hisashi Tsuruoka

Kimio Ooe

Tuneo Funabashi

A physical space management table is disposed outside the microprocessor in order to hold attribute data of the regions of the physical space held as a set of a plurality of regions in a manner corresponding to the regions of the physical space. The microprocessor is provided with a physical space management unit which fetches the attribute data from the physical space management table and manages them. The physical space management unit includes a physical space management table search control circuit, and a physical data buffer which primarily holds the attribute data obtained by the physical space management table search control circuit and the physical address in a manner corresponded to each other.

Microprocessor and storage management system having said microprocessor

An address translation apparatus which includes a memory for storing a plurality of physical addresses, and a content addressable memory unit which stores a plurality of signal pairs that correspond to the plurality of physical addresses, each of the signal paris includes a logical address that corresponds to one of the plurality of physical addresses and memory protection level data that indicates a memory protection level allocated to a memory position of the one of the physical addresses. The content addressable memory unit includes apparatus for searching a signal pair that has a logical address in coincident with a logical address being subjected to address translation and comparing memory protection level data to comparative data at a bit position which is indicated to be the bit position to be searched by mask data, in response to the logical address translation. The mask data instructs whether the bits of the stored memory protection level data are to be searched, wherein mask data is determined depending upon a memory access privilege level allocated to a program that requests address translation, and whether comparative data are to be compared with the stored memory protection level data. The content addressable memory further includes apparatus for instructing the memory to produce a physical address that corresponds to the detected signal pair.

Address translation apparatus having a memory access privilege check

A memory management device which is connected in a virtual address space or a physical address space together with another device capable of becoming a bus master, is endowed with the function of detecting the bus request signal of the other device, interrupting an address translation process under execution and causing a processor to release a bus. Thus, the other device can be made the bus master without being kept waiting for a long time, and a system bug can be prevented which is attributed to such a fact that a wait time exceeds the data hold time of an input/output device connected to, for example, a direct memory access controller.

Memory management device

In a multiprocessor system having a hierachal memory device employing a virtual memory system, serial communication means which makes it possible for memory management units, which are disposed for CPUs, respectively, to communicate with one another, so that any change of common memory management information can be exchanged directly between the memory management units. As a result, it is not necessary for each CPU to inform the memory management unit of any change of the memory management information by an operating system, so that the overhead of communication between CPUs can be reduced and memory management can be made correctly without applying any load to the operating system even when any change occurs in the memory management information.

Memory management unit

A content-addressed memory which has a priority ranking circuit and/or a write control circuit provided in an output section thereof, the priority ranking circuit being adapted to be selectively operated so as to selectively output only one hit signal and the write control circuit being adapted to receive a hit signal and allow a corresponding memory cell to be brought into a write enable state.

Content-addressed memory

An address information line of a microprocessor informs a memory management unit of such address information that a current address is identical to an address before one bus-cycle or two bus-cycles or is a new address. Since the address information line has a light load, the address information is transmitted at high speed. In addition, if the current address is identical to the address before one or several bus-cycles, address conversion within the memory management unit can be quickened in such a way that these addresses are temporarily stored in the memory management unit, whereupon the corresponding address is read out.

Microcomputer system for high speed address translation

An address translation unit for use in a computer system having a multi-virtual space comprises a full associative translation lookaside buffer (TLB) which includes, for each entry, an associative memory array which stores and compares addresses. The associative memory array is provided with a circuit which, when a specific value is set in a common area field, invalidates comparison in a space number field.

Address translation unit

A static RAM having a plurality of memory cells. Each memory cell consists of driver MOST's that are connected to each other in a crossing manner, and transfer MOST's that connect storage nodes of the memory cell to the data lines. The driver MOST's are comprised of n-channel MOST's, and the transfer MOST's are comprised of p-channel MOST's.

Random access memory with high density and low power

A pulse width modulation circuit which can cancel the mean error of pulse width modulation with respect to time due to the offset voltage of a triangular wave signal and to the offset voltage of a comparator, by adding simple circuits to an existing pulse width modulation circuit. The invention relates also to an integration circuit of the product of two analog signals using the pulse width modulation circuit described above. The principle of the present invention combines a circuit for cancelling the offset of a triangular wave signal by inverting either the triangular wave signal with respect to an input signal or the input signal with respect to the triangular wave signal, in every predetermined period, with a circuit for eliminating the offset of a comparator by inverting the output of the comparator and replacing the input terminals of the comparator if the input signal is not inverted, or connecting the input terminal of the comparator as such if the input signal is inverted.

Pulse width modulation circuit and integration circuit of analog product

An integrator circuit comprising reset means by which, when it is detected that an integrator output V.sub.p for an input analog signal coincides with a plus or minus reference value, the integral output is reset to the vicinity of the middle of the plus and minus reference values, in effect, without interrupting the integrating operation; a circuit which produces a pulse each time coincidence is detected; and a circuit which produces a direction signal indicating whether the coincidence results from an increase or a decrease of the integral input. The pulses produced in the state in which the direction signal is indicating an increase are counted up, and the pulses produced in the state in which the direction signal is indicating a decrease are counted down, whereby the precise integral value of the input analog signal can be detected.

Circuit for integrating analog signal and converting it into digital

An analog-to-digital converter includes a capacitor array circuit for determining m upper bits of a digital output, which includes a plurality of capacitors having binary-weighted capacitance ratios and a plurality of switches and which is connected to an input terminal of a sampled analog voltage and a reference voltage source. A resistor string circuit is provided for determining n lower bits of the digital output, including a plurality of switches and which is connected to the capacitor array circuit. A voltage comparator compares an output voltage of the capacitor array circuit with the ground potential and successive approximation registers successively provide pulses for controlling the switches of the capacitor array circuit and the resistor string circuit in accordance with the output of the voltage comparator. A circuit generates timing pulses for controlling the operation of the successive approximation registers. The resistor string circuit applies voltages equal to i/2.sup.n (where i denotes a value expressed by the n lower bits of the digital output) and (2.sup.n -i)/2.sup.n of a reference voltage to the capacitor array circuit, and the capacitor array circuit operates so as to put the input analog signal into a digital signal in accordance with a linear input/output conversion characteristic.

Signal converter

A signal converter includes a generator for generating first and second clock signals having recurrence periods equal to each other and phases different from each other, an input for receiving as a signal to be converted a signal which has signal levels not lower than a predetermined level during an arbitrary period of time, a counter for counting the first clock signals from the generator in a period of time corresponding to the signal period of time, and an output arrangement. The output arrangement provides for delivering either of two signals in dependence on which of time intervals determined by the first and second clock signals an end of said signal period of time lies in, whereby signals of the counter and the output arrangement are used as a converted signal.

Signal converter utilizing two clock signals

An analog-to-digital converter comprising a capacitor for storing an analog input signal, a constant current discharging circuit coupled with the capacitor for discharging the charge stored therein, a level detection circuit connected to the input terminal of the capacitor, a counter connected to the output terminal of the level detection circuit for counting the number of clock-pulses between the time of discharge start and the time when the voltage at the input terminal of the capacitor drops to a detection level of the level detection circuit, a bias voltage supply means connected in series with the capacitor for adding a bias voltage to the voltage at the input terminal of said capacitor, and a switch connected in parallel with the capacitor for short-circuiting the capacitor when the voltage at the input terminal of said capacitor drops to the detection level.

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Higashimurayama, Japan

Katsuaki Takagi