Micron Technology Incorporated

Katie Blomster Park

Vijay S Ramesh

Reshmi Basu

Richard Donald Maes, Ii

Gary A Johnson

Robert J Pintar

Systems, apparatuses, and methods related to bit string accumulation are described. A method for bit string accumulation can include performing an iteration of a recursive operation using a first bit string and a second bit string and modifying a quantity of bits of a result of the iteration of the recursive operation, wherein the modified quantity of bits is less than a threshold quantity of bits. The method can further include writing a first value comprising the modified bits indicative of the result of the iteration of the recursive operation to a first register and writing a second value indicative of the factor corresponding to the result of the iteration of the recursive operation to a second register.

Bit string accumulation

A method is described that includes receiving a write request with user data and a logical address and select a next address queue from a plurality of next address queues based on a reciprocal relationship between short-term usage information associated with the logical address and a set of characteristics of the selected next address queue. Each next address queue in the plurality of next address queues stores physical addresses that are designated to be used for fulfilling write requests. Further, a next physical address is removed from the selected next address queue and the user data of the write request is written to the next physical address in a memory device.

Profile and queue-based wear leveling of memory devices

A method for wear leveling memory elements in a memory component of a memory subsystem is described. The method includes a memory subsystem receiving a write request that includes user data and a logical address, removing a next physical address from a next address queue, which stores physical addresses that are designated to be used for fulfilling write requests, and writing the user data to the next physical address in the memory component. Further, the memory subsystem locates, in a logical-to-physical table, an entry associated with the logical address of the write request and includes an old physical address that is mapped to the logical address of the write request. The memory subsystem adds the old physical address to a disposal address queue, wherein the disposal address queue stores physical addresses that are not designated to be used for fulfilling write requests.

Queue-based wear leveling of memory components

Systems, apparatuses, and methods related to bit string conversion are described. Circuitry can perform operations on bit strings, such as universal number and/or posit bit strings, to alter a level of precision (e.g., a dynamic range, resolution, etc.) of the bit strings. For instance, bit string conversion can include receiving, by a memory resource coupled to logic circuitry, a first bit string having a first bit string length. The first quantity of bits can comprise a first bit sub-set, a second bit sub-set, a third bit sub-set, and a fourth bit sub-set. The logic circuitry monitor numerical values corresponding to at least one bit sub-set of the bit string to determine a dynamic range corresponding to the data and/or precision corresponding to the data and generate a second bit string having a second bit string length based, at least in part, on the determined dynamic range of the data, the precision of the data.

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Liberty Lake, WA, United States of America

Katie Blomster Park