International Business Machines Corporation

Kathryn Wilder Guarini

Meikei Ieong

Charles Thomas Black

Kevin K Chan

Paul Michael Solomon

Bruce Bennett Doris

Guy M Cohen

Cyril Cabral, Jr

Christian Lavoie

Min Yang

Leathen Shi

Erin C Jones

Huiling Shang

David James Frank

Sampath Purushothaman

Kern Rim

Jack Oon Chu

Matthew Earl Colburn

Omer H Dokumaci

Satya Venkata Nitta

Dinkar Virendra Singh

David V Horak

Steven J Holmes

Jeffrey W Sleight

Toshiharu Furukawa

Mark Charles Hakey

Ying Di Zhang

Shreesh Narasimha

Eduard Albert Cartier

Mark Alan Lavin

Hon-Sum Philip Wong

Fenton Read McFeely

Christopher Bruce Murray

Xinlin Wang

Prabhakar Nandavar Kudva

Ibrahim M Elfadel

Ronnen Andrew Roy

David Shing-Ki Kung

Suryanarayan G Hegde

William Hsioh-Lien Ma

Douglas A Buchanan

Keith Raymond Milkove

John J Yourkas

Syed M Alam

Arifur Rahman

Antonio F Saavedra, Jr

Louis L Hsu

Li-Kong Wang

Victor Chan

Roy Arthur Carruthers

James M Harper

Suryanararyan G Hegde

Meikel Ieong

A method of making a nanoparticle array that includes replicating a dimension of a self-assembled film into a dielectric film, to form a porous dielectric film, conformally depositing a material over the said porous dielectric film, and anisotropically and selectively etching the deposited material.

Nonvolatile memory device using semiconductor nanocrystals and method of forming same

A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.

Interconnect structures with engineered dielectrics with nanocolumnar porosity

A method of making a nanoparticle array that includes replicating a dimension of a self-assembled film into a dielectric film, to form a porous dielectric film, conformally depositing a material over said porous dielectric film, and anisotropically and selectively etching said deposited material.

Nonvolatile memory device using semiconductor nanocrystals and method forming same

A method of making a uniform nanoparticle array, including performing diblock copolymer thin film self assembly over a first dielectric on silicon, creating a porous polymer film, transferring a pattern into the first dielectric, selectively growing epitaxial silicon off a silicon substrate from within pores to create a silicon nanoparticle array.

Nonvolative memory device using semiconductor nanocrystals and method of forming same

A floating gate for a field effect transistor (and method for forming the same and method of forming a uniform nanoparticle array), includes a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of the nanoparticles is one of templated and defined by a self-assembled material.

Method of forming a nonvolatile memory device using semiconductor nanoparticles

A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

Self-aligned planar double-gate transistor structure

A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.

Integration of strained Ge into advanced CMOS technology

A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Three dimensional integrated circuit and method of design

An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.

High-performance CMOS SOI devices on hybrid crystal-oriented substrates

Described is a wet chemical surface treatment involving NHOH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO) at low temperatures (less than or equal to 400&#xb0; C.). Surface energies as high as &#x2dc;4835&#xb1;675 mJ/mof the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000&#xb0; C.). Void free bonding interfaces with excellent yield and surface energies of &#x2dc;2500 mJ/mhave also be achieved herein.

Low temperature fusion bonding with high surface energy using a wet chemical treatment

A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal layer, etching anisotropically and selectively with respect to the metal the silicon layer, reacting the metal with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal layer, annealing at a second temperature to form an alloy of metal-Si, and selectively etching the unreacted silicon layer.

Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby

A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer: a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

Growing community of inventors

Yorktown Heights, NY, United States of America

Kathryn Wilder Guarini