International Business Machines Corporation

Globalfoundries Inc.

Barcelona Supercomputing Center-centro Nacional De Supercomputacion

Barcelona Supercomputing Center

Kathryn Mary O'Brien

John Kevin O'Brien

John Kevin Patrick O'Brien

Tong Chen

Alexandre E Eichenberger

John K P O'Brien

Tao Zhang

Mark Richard Nutter

Brian King Flachs

Brad William Michael

Daniel Arthur Prener

Michael K Gschwind

Ravi Nair

Peter Howland Oden

Valentina Salapura

Zehra Noman Sura

Xiaotong Zhuang

Erik Richter Altman

Nicolas T Vasilache

Alan G Gara

Martin Ohmacht

Sumedh Wasudeo Sathaye

Marc Gonzalez Tallada

Dong Chen

Paul William Coteus

Michael A Blocksome

Joseph D Ratterman

Philip Heidelberger

Adam James Muff

Todd Edward Takken

Bruce Martin Fleischer

Robert William Wisniewski

Thomas M Gooding

John A Gunnels

Mark Edwin Giampapa

Burkhard Steinmacher-Burow

Mark Gregory Megerian

Sameh W Asaad

Matthias Augustin Blumrich

Shawn Anthony Hall

Thomas Winters Fox

Chen-Yong Cher

Barry Marshall Trager

Peng Wu

Charles David Wait

Sameer Kumar

James Anthony Marcella

Todd Alan Inglett

George L Chiu

Krishnan Sugavanam

Gerard Vincent Kopcsay

Jeffrey John Parker

Robert Matthew Senger

Noel A Eisley

David L Satterfield

Douglas R Miller

Craig Brian Stunkel

Rudolf Adriaan Haring

Amith R Mamidala

Yutaka Sugawara

Kristan D Davis

Jose R Brunheroto

Michael B Mundy

Matthew Roger Ellavsky

Robert E Walkup

James Lee Van Oosten

Samuel J Miller

Gabor J Dozsa

Ruth Janine Poole

Peter Boyle

Brant L Knudson

Ralph E Bellofatto

Norman Christ

Kahn C Evans

William Maupin Stockdell

Alfred Thomas Watson, Iii

Byoungro So

Eduard Ayguade

Xavier Martorell

Brian E Smith

Michael Norman Day

Kai-Ting Amy Wang

Lakshminarayanan Renganarayana

Linh Hue Lam

Chiao-Mei Chuang

Pradeep Kumar Dubey

Charles Marshall Barton

Sumeda Wasudeo Sathaye

Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device.

Arranging binary code based on call graph partitioning

According to one embodiment, a method of creating compiler-generated memory mapping hints in a computer system includes analyzing code, by a compiler of the computer system, to identify data access patterns in the code. System configuration information defining data processing system characteristics of a target system for the code is accessed. The data processing system characteristics include a plurality of processing resources and memory domain characteristics relative to the processing resources. A preferred allocation of data in memory domains of the target system is determined based on mapping the code to one or more selected processing resources and mapping the data to one or more of the memory domains based on the memory domain characteristics relative to the one or more selected processing resources. The preferred allocation is stored as compiler-generated memory mapping hints in a format accessible by a physical memory mapping resource of the target system.

Compiler-generated memory mapping hints

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Multi-petascale highly efficient parallel supercomputer

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

A method (and system) of emulation in a multiprocessor system, includes performing an emulation in which a host multiprocessing system of the multiprocessor system supports a weak consistency model, and the target multiprocessing system of the multiprocessor system supports a strong consistency model.

Method and system for efficient emulation of multiprocessor memory consistency

Partitioning programs between a general purpose core and one or more accelerators is provided. A compiler front end is provided for converting a program source code in a corresponding high level programming language into an intermediate code representation. This intermediate code representation is provided to an interprocedural optimizer which determines which core processor or accelerator each portion of the program should execute on and partitions the program into sub-programs based on this set of decisions. The interprocedural optimizer may further add instructions to the partitions to coordinate and synchronize the sub-programs as required. Each sub-program is compiled on an appropriate compiler backend for the instruction set architecture of the particular core processor or accelerator selected to execute the sub-program. The compiled sub-programs and then linked to thereby generate an executable program.

Method for partitioning programs between a general purpose core and one or more accelerators

Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the current cache line. A determination is made as to whether the current cache line is to be evicted from the instruction cache. The linked list of call sites is processed to identify one or more rewritten branch instructions having associated branch stubs, that either directly or indirectly target the portion of code in the current cache line. In addition, the one or more rewritten branch instructions are rewritten to restore the one or more rewritten branch instructions to an original state based on information in the associated branch stubs.

Dynamically rewriting branch instructions in response to cache line eviction

A method (and structure) of mapping a memory addressing of a multiprocessing system when it is emulated using a virtual memory addressing of another multiprocessing system includes accessing a local lookaside table (LLT) on a target processor with a target virtual memory address. Whether there is a 'miss' in the LLT is determined and, with the miss determined in the LLT, a lock for a global page table is obtained.

Method and system for efficient emulation of multiprocessor address translation on a multiprocessor

Mechanisms are provided for rewriting branch instructions in a portion of code. The mechanisms receive a portion of source code having an original branch instruction. The mechanisms generate a branch stub for the original branch instruction. The branch stub stores information about the original branch instruction including an original target address of the original branch instruction. Moreover, the mechanisms rewrite the original branch instruction so that a target of the rewritten branch instruction references the branch stub. In addition, the mechanisms output compiled code including the rewritten branch instruction and the branch stub for execution by a computing device. The branch stub is utilized by the computing device at runtime to determine if execution of the rewritten branch instruction can be redirected directly to a target instruction corresponding to the original target address in an instruction cache of the computing device without intervention by an instruction cache runtime system.

Rewriting branch instructions using branch stubs

Mechanisms for building approximate data dependences using a moving look-back window are provided. The mechanisms track dependence information for memory accesses over iterations of execution of a portion of code. The mechanisms receive a memory access of an iteration of the portion of code, the memory access having an address for access the memory and an access type indicating at least one of a read or a write access type. An entry in a moving look-back window data structure is generated corresponding to a memory location accessed by the memory access. The entry comprises at least an identification of the address, the access type, and an iteration number corresponding to the iteration of the memory access. The moving look-back window data structure is utilized to determine dependence information for memory accesses over a plurality of iterations of the portion of code.

Building approximate data dependences with a moving window

Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache.

Dynamically rewriting branch instructions to directly target an instruction cache location

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South Salem, NY, United States of America

Kathryn Mary O'Brien