International Business Machines Corporation

Advanced Micro Devices Corporation

Kathryn Jean Hoover

Richard T Witek

Stephen Charles Kromer

Carl D Dietz

James Joseph Montanaro

Suzanne Plummer

An integrated circuit () includes a firewall input terminal, a first circuit (), and a second circuit (). The firewall input terminal is for receiving a firewall input signal. The first circuit () is coupled to a first power supply voltage terminal () and has an output for providing a control signal. The second circuit is coupled to a second power supply voltage terminal (), to the firewall input terminal (), and to the first circuit (). When the firewall input signal is inactive, an activation of the control signal affects the operation of the second circuit. When the firewall input signal is active, an activation of the control signal does not affect the operation of the second circuit.

Integrated circuit with a hibernate mode and method therefor

A data processing system () comprises a system bus (), a plurality of devices () coupled to the system bus (), a bus monitor circuit (), and a clock generator (). The plurality of devices () includes at least one bus master () which is capable of performing accesses on the system bus (). The bus monitor circuit () is coupled to the at least one bus master (), and has an output for providing a bus idle signal to indicate that no bus master is attempting to perform an access on the system bus (). The clock generator () has an output coupled to at least one of the plurality of devices () and provides a bus clock signal having a first frequency when the bus idle signal is inactive and having a second frequency lower than the first frequency when the bus idle signal is active.

Method and apparatus for lowering bus clock frequency in a complex integrated data processing system

Content addressable memory circuitry and a method of operation are provided. First information is stored. A logic state of a first match line is selectively modified in response to a comparison between the first information and second information. Also, third information is stored. A logic state of a second match line is selectively modified in response to a comparison between the third information and fourth information. A logic state of the second match line is selectively modified in response to the logic state of the first match line.

Content addressable memory circuitry and method of operation

Comparator circuitry and a method of operation are provided. First and second match lines are precharged. First and second information are compared, and the first match line is selectively discharged in response thereto. Third and fourth information are compared, and the second match line is selectively discharged in response thereto. The second match line is discharged in response to discharging the first match line.

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Austin, TX, United States of America

Kathryn Jean Hoover