Freescale Semiconductor,inc.

Motorola Corporation

Kathleen C Yu

Hector Adrian Sanchez

Janos Farkas

Byoung W Min

Yeong-Jyh Tom Lii

Michael A Mendicino

Kirk J Strozewski

Nigel Graeme Cave

Bradley P Smith

Olubunmi O Adetutu

Edward Outlaw Travis, Jr

Robert E Jones

Stanley Michael Filipiak

Terry Grant Sparks

Robert L Maziasz

Scott Daniel Hector

John C Flake

Claudia A Stanley

Yuri Solomentsev

Lynne M Michaelson

Cindy K Goldberg

James E Vasck

Robert E Jones Jr

A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.

Method of area compaction for integrated circuit layout design

A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.

Semiconductor device having a multiple thickness interconnect

A semiconductor () has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (), that are connected by a via or conductive region () and interconnect (). The via or conductive region () contacts a bottom surface of a diffusion or source region () of the transistor and contacts a first () of the capacitor electrodes. A laterally positioned vertical via () and interconnect () contacts a second () of the capacitor electrodes. A metal interconnect or conductive material () may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.

Semiconductor device including a transistor and a capacitor having an aligned transistor and capacitive element

One embodiment forms a gate dielectric layer over a substrate and then selectively deposits a first metal layer over portions of the gate dielectric layer in which a first device type will be formed. A second metal layer, different from the first metal layer, is formed over exposed portions of the gate dielectric layer in which a second device type will be formed. Each of the first and second device types will have different work functions because each will include a different metal in direct contact with the gate dielectric. In one embodiment, the selective deposition of the first metal layer is performed by ALD and with the use of an inhibitor layer which is selectively formed over the gate dielectric layer such that the first metal layer may be selectively deposited on only those portions of the gate dielectric layer which are not covered by the inhibitor layer.

Method for forming a gate electrode having a metal

Semiconductor device having electrical contact from opposite sides including a via with an end formed at a bottom surface of the diffusion region

Dummy features () are formed within an interlevel dielectric layer (). Passivation layers (and) are formed by electroless deposition to protect the underlying conductive regions (and) from being penetrated from the air gaps (). In addition, the passivation layers (and) overhang the underlying conductive regions (and), thereby defining dummy features (and) adjacent the conductive regions (and). The passivation layers (and) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.

Method for forming a passivation layer for air gap formation

Method for forming a semiconductor device having electrical contact from opposite sides

Method for forming a semiconductor interconnect with multiple thickness

Dummy features ( ) are formed within an interlevel dielectric layer ( ). A non-gap filling dielectric layer ( ) is formed over the dummy features ( ) to form voids ( ) between dummy features ( ) or between a dummy feature ( ) and a current carrying region ( ). The dummy features ( ) can be conductive ( ) and therefore, formed when forming the current carrying region ( ). In another embodiment, the dummy features ( ) are insulating ( ) and are formed after forming the current carrying region ( ). In yet another embodiment, both conductive and insulating dummy features ( ) are formed. In a preferred embodiment, the voids ( ) are air gaps, which are a low dielectric constant material.

Method for providing a dummy feature and structure thereof

In one embodiment of the invention, conductive support structures (,) are formed within an interlevel dielectric layer. The conductive support structures (,) lie within the bond pad region (,) of the integrated circuit and provide support to portions of the interlevel dielectric layer that have a low Young's modulus. The conductive support structures (,) are formed using the same processes that are used to form metal interconnects in the device region (,) of the integrated circuit, but they are not electrically coupled to semiconductor devices that lie within the device region (,). Conductive support structures (,) are also formed within the scribe line region (,) to provide support to the interlevel dielectric layer in this region of the integrated circuit.

Method for forming a semiconductor device

In one embodiment of the invention, conductive support structures (112) are formed within an interlevel dielectric layer. The conductive support structures (112) lie within the bond pad region (111) of the integrated circuit and provide support to portions of the interlevel dielectric layer that have a low Young's modulus. The conductive support structures (112) are formed using the same processes that are used to form metal interconnects in the device region (109) of the integrated circuit, but they are not electrically coupled to semiconductor devices that lie within the device region (109). Conductive support structures (114) are also formed within the scribe line region (104) to provide support to the interlevel dielectric layer in this region of the integrated circuit.

Integrated circuit having a support structure

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Austin, TX, United States of America

Kathleen C Yu