Seagate Technology Incorporated

Ess Technology, Inc.

Pictos Technologies, Inc.

Kathleen Anne Duncan

Prafulla Bollampalli Reddy

Don M Robinson

William S Jacobs

Raymond S Livingston

Marvin Mang-Yin Lum

Robert G Taylor

A programmable image transform system has a programmable addressing and arithmetic blocks. In the programmable addressing block, an input address generator has an input addressing microsequencer and an input addressing memory that stores an input addressing procedure. The microsequencer executes the input addressing procedure to generate addresses from which to request image data. In the programmable arithmetic block, an arithmetic block memory stores an image processing procedure and a microsequencer executes the image processing procedure using the image data to generate transformed image data.

Programmable image transform processor

A programmable image transform processor has a programmable addressing and arithmetic blocks. In the programmable addressing block, an input address generator has an input addressing microsequencer and an input addressing memory that stores an input addressing procedure. The microsequencer executes the input addressing procedure to generate addresses from which to request image data. In the programmable arithmetic block, an arithmetic block memory stores an image processing procedure and a microsequencer executes the image processing procedure using the image data to generate transformed image data.

Programmable image transform processor for digital image processing

A modular ATA hard disc controller includes a small on-chip ATA sequencer microprocessor having on-chip dedicated hardware to manage real-time events without host CPU intervention, without substantially degrading cost/performance for the resultant controller chip. To conserve IC chip space, a small instruction set for the on-chip ATA sequencer microprocessor is provided, wherein branch instructions are avoided. The instruction set causes execution only for a given data transfer direction (read or write), or executes always. On-chip task registers are coupled directly to the ATA sequencer microprocessor. This architecture minimizes host CPU bottlenecking by decoupling the host CPU from real-time events occurring on the AT bus, and by decoupling the local processor from the task registers. The resultant controller automatically receipts for all write data, handles task file updating and intersector handshaking, and host microprocessor queueing of the address of the next disc data block to be transferred.

System including ATA sequencer microprocessor which executes sequencer

A disc controller services a host 'read' command, without intervention by the disc controller's microcontroller, if the requested data is found in the disc controller's cache. The disc controller stores at least one cache entry. Each cache entry includes an address, a logical Bit, a valid Bit and a set of four buffer parameters: upper limit address, base address, pointer to the sector count and sector count. Each host command is decoded by the disc controller, and if the command is a 'read' command the address in the cache entry is compared against the address in the host command. If the addresses match and the cache entry address is marked as being valid by its Valid bit, a 'cache hit' signal is generated and the disc controller starts transferring the data requested by the host without waiting for the disc controller's microprocessor to process the host command. In particular, a sequencer and data transfer circuitry automatically generate a host interrupt request signal and transfer to the host at least a subset of the requested set of data blocks specified by each read command when a cache hit signal is generated. The disc controller includes circuitry for updating the information stored in the cache entry so that said updated information stored in the cache entry identifies data blocks in the cache sequentially subsequent to those data blocks transferred to the host.

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Santa Cruz, CA, United States of America

Kathleen Anne Duncan