Texas Instruments Corporation

Katherine E Violette

Rick L Wise

Douglas Ticknor Grider

Stanton Petree Ashburn

Mark Stephen Rodder

Mahalingam Nandakumar

Rajesh B Khamankar

Antonio L P Rotondaro

Francis Gabriel Celii

Robert Kraft

F Scott Johnson

Darius Lammont Crenshaw

Ih-Chin Chen

Reima Tapani Laaksonen

Sreenath Unnikrishnan

Maureen A Hanratty

Chih-Ping Chao

Aditi D Banerjee

Rebecca J Gale

Charlotte M Appel

A method of determining the thickness of a thickness of a first layer of material in a semiconductor device using a reflectometer, the first layer of material being disposed outwardly from a second layer of material, the first and second layer of material both including silicon. The method includes generating at least one predicted behavior curve associated with a depth profile of an interface between the first and second layer of material, the predicted behavior curve including at least one expected optical measurement, the depth profile associated with the interface being present at a particular theoretical depth. The method also includes emitting light onto a surface of the semiconductor device. The method further includes collecting at least one optical measurement from portions of the emitted light that are reflected by the semiconductor device. The method additionally includes comparing the at least one optical measurement to the predicted behavior curve and determining the approximate actual depth of the interface in response to the compared optical measurement.

Process for monitoring the thickness of layers in a microelectronic device

Silicon substrate isolation by epitaxial growth of silicon through windows in a mask made of silicon nitride (,) on silicon oxide (,) with the silicon oxide etched to undercut the silicon nitride; the mask is on a silicon substrate.

Integrated circuit isolation

Sidewall spacers extending above a silicon gate with the distance between the spacers exceeding the length of the gate are used to confine selective silicon growth of the gate and subsequent self-aligned silicidation.

Integrated circuit and method

A method of forming a plurality of shallow junction transistors, the method comprising the steps of providing a substrate (,) having a first region (,) and a second region (,). The first region (,) and the second region (,) include a first channel region (,) and a second channel region (,), respectively. A first gate (,) is formed proximate the first channel region (,) and is separated from the substrate (,) by a portion of a primary insulation layer (,). A second gate (,) is formed proximate the second channel region (,) and is separated from the substrate by a portion of the primary insulation layer (,). A dopant layer (,) is then formed outwardly of the substrate (,) proximate the first region (,) and the second region (,). The dopant layer (,) proximate the first region (,) is implanted with a first dopant (,). The dopant layer (,) proximate the second region (,) is implanted with a second dopant (,). A portion of the first dopant (,) in the dopant layer (,) is diffused into the substrate (,) proximate the first region (,) to form a first shallow doped region (,), and a portion of the second dopant (,) in the dopant layer (,) is diffused into the substrate (,) proximate the second region (,) to form a second shallow doped region (,). The first shallow doped region (,) may form a source and a drain for a first shallow junction transistor (,) and the second shallow doped region (,) may form a source and a drain for a second shallow junction transistor (,).

Method of fabricating a shallow doped region for a shallow junction transistor

A plasma process is described which produces an undamaged and uncontaminated silicon surface by consuming silicon by continuous oxidation through a surface oxide layer and a simultaneous etch of the exposed silicon oxide surface. The surface silicon dioxide layer thickness is controlled as an equilibrium between oxide growth from oxygen atoms reaching the silicon surface and etching of the oxide surface. The silicon dioxide protects the silicon surface from plasma damage and from contamination.

Silicon processing method

A rugged polysilicon electrode for a capacitor has high surface area enhancement with a thin layer by high nucleation density plus gas phase doping which also enhances grain shape and oxygen-free dielectric formation.

Capacitor and memory structure and method

An embodiment of the instant invention is a method of fabricating a semiconductor device which includes a dielectric layer situated between a conductive structure and a semiconductor substrate, the method comprising the steps of: forming the dielectric layer (layer 14) on the semiconductor substrate (substrate 12); forming the conductive structure (structure 18) on the dielectric layer; doping the conductive structure with boron; and doping the conductive structure with a dopant which inhibits the diffusion of boron. The semiconductor device may be a PMOS transistor or a capacitor. Preferably, the conductive structure is a gate structure. The dielectric layer is, preferably, comprised of a material selected from the group consisting of: an oxide, an oxide/oxide stack, an oxide/nitride stack, and an oxynitride. Preferably, the dopant which inhibits the diffusion of boron comprises at least one group III or group IV element. More specifically, it is preferably comprised of: carbon, germanium, and any combination thereof. Preferably, the steps of doping the conductive structure with boron and doping the conductive structure with a dopant which inhibits the diffusion of boron are accomplished substantially simultaneously, or the step of doping the conductive structure with boron is preformed prior to the step of doping the conductive structure with a dopant which inhibits the diffusion of boron are accomplished substantially simultaneously.

Doped polysilicon to retard boron diffusion into and through thin gate

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Dallas, TX, United States of America

Katherine E Violette