Sperry Corporation

Katherine A Splett

Gerald L Brown

James A Howe

Steven H Karban

A timing generator and verifier is provided in which a PROM stores the timing constants that are employed by the generator. An address counter, which is driven by a clock timer, cycles through an associated portion of the PROM to provide a sequence of output signals which represent timing for a particular mode. If a different mode is selected, the address counter selects a different sequence of output bits. During Normal mode the address counter operates on a cyclic basis driven by a fixed frequency free running master clock. In Verify mode the address counter is stepped by the Host computer. The outputs of the PROM are coupled through a buffer and logic section, where the outputs may be modified before being coupled to an adder which accumulates a checksum based on the outputs of all of the bits for a particular selected timing. The checksum provided by the adder is compared in a comparator with a stored checksum that indicates whether the correct operation of the complex timing cycle for the selected mode has been verified.

Generation and diagnostic verification of complex timing cycles

A synchronous clock circuit is provided on each module of an electronic digital system formed of a plurality of modules. Each clock circuit has two control pins which are used by control logic to determine whether or not the clock on a particular module is disabled, is operating as the master clock for the system, or is providing a backup function for the master clock. The common clock line is supplied through a buffer to the components on the module which require clocking. Logic circuitry on the backup clock mode insures the backup clock is in a ready condition in case there should be either failure of the master clock oscillator or if the master clock module is removed from the unit. All of the clock circuits of the different modules may be constructed in an identical manner, with the control of the function of the circuitry being provided simply by control of the logic level on the two terminals. A clock detecting time-out circuit is provided on each of the modules, which has a timing period which is slightly longer than the clock period. If the master clock fails to produce a clock pulse at the time that it should, the clock detect timing circuit, which is coupled to the buffer of the backup module, will sense that a failure has occurred and will control the turn-on of the clock circuit for the backup module.

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Burnsville, MN, United States of America

Katherine A Splett