Infineon Technologies Dresden Gmbh & Co . Kg

Infineon Technologies Austria Ag

Infineon Technologies Dresden Gmbh

Katarzyna Kowalik-Seidl

Markus Schmitt

Rolf Weis

Winfried Kaindl

Bjoern Fischer

Matthias Wegscheider

Franz Hirler

Anton Mauder

Joachim Weyers

Armin Tilke

Uwe Wahl

Enrique Vecino Vazquez

Marco Mueller

Andreas Schloegl

Björn Fischer

Richard Hensch

Olaf Fiedler

Daniel Kai Simon

Ayad Abdul-Hak

Markus Wiesinger

Anthony Sanders

A transistor arrangement is disclosed. The transistor arrangement includes a first transistor device and a second transistor device. The first transistor device and the second transistor device are connected in series and integrated in a common semiconductor body. The first transistor device is a lateral superjunction transistor device and is integrated in a first device region of the semiconductor body. The second transistor device is a lateral transistor device and is integrated in at least one second device region of the semiconductor body. The at least one second device region is spaced apart from the first device region.

Transistor arrangement with a lateral superjunction transistor device

A semiconductor device includes a semiconductor body having first and second opposing surfaces in a vertical direction, and transistor cells at least partly integrated in the semiconductor body. Each transistor cell includes first and second source regions, first and second body regions, a drift region separated from the respective source region by the corresponding body region, a first gate electrode, and a control electrode. The drift region is arranged between the first and the second body region in a horizontal direction that is perpendicular to the vertical direction and extends from the first surface into the semiconductor body in the vertical direction. The first gate electrode is configured to provide a control signal for switching the transistor cell. The control electrode is configured to provide a control signal for controlling a JFET formed by the first body region, the drift region, and the second body region.

Semiconductor device

A transistor device includes at least one transistor cell, having, in a semiconductor body, a source region of a first doping type in a body region of a second doping type, a drain region, and a drift region of the first doping type adjoining the body region and arranged between the body region and the drain region. A low-resistance region of the second doping type in the body region adjoins the source region. A gate electrode dielectrically insulated from the source and body regions by a gate dielectric is arranged above a first surface of the semiconductor body. A length of an overlap between the source region and the gate electrode is larger than 70 nanometers. A doping profile of the low-resistance region along a line that is vertical to the first surface and goes through an edge of the gate electrode has a maximum of higher than 1E19 cm.

Latch-up resistant transistor device

A semiconductor device include a semiconductor body with a drain region of a first conductivity type, a drift region of the first conductivity type and having a doping concentration lower than a doping concentration of the drain region, a buffer region of the first conductivity type arranged between the drift region and the drain region, a source region of the first conductivity type, a body region of a second conductivity type arranged between the source region and the drift region and forming a first pn-junction with the source region and a second pn-junction with the drift region, and a charge compensation region of the second conductivity type extending from the body region towards the buffer region. A source metallization is in ohmic contact with the source region. A drain metallization is ohmic contact with the drain region.

Semiconductor device with buffer region

A semiconductor device includes a semiconductor body. The semiconductor body has a first surface and a second surface opposite to the first surface. A transistor cell structure is provided in the semiconductor body. A gate contact structure includes a gate line electrically coupled to a gate electrode layer of the transistor cell structure, and a gate pad electrically coupled to the gate line. A gate resistor structure is electrically coupled between the gate pad and the gate electrode layer. An electric resistivity of the gate resistor structure is greater than the electric resistivity of the gate electrode layer.

Semiconductor device including a gate contact structure

Disclosed is a method for producing a transistor device and a transistor device. The method includes: forming a source region of a first doping type in a body region of a second doping type in a semiconductor body; and forming a low-resistance region of the second doping type adjoining the source region in the body region. Forming the source region includes implanting dopant particles of the first doping type using an implantation mask via a first surface of the semiconductor body into the body region. Implanting the doping particles of the first doping type includes a tilted implantation.

Latch-up resistant transistor

A semiconductor device includes transistor cells with vertical channels perpendicular to a first surface of a semiconductor portion. A buried compensation structure in the semiconductor portion between the transistor cells and a second surface of the semiconductor portion parallel to the first surface includes first areas and second areas. The first and second areas are alternatingly arranged along a lateral direction parallel to the first surface. A contiguous impurity layer of a first conductivity type separates the transistor cells from the buried compensation structure.

Semiconductor device with vertical transistor channels and a compensation structure

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Munich, Germany

Katarzyna Kowalik-Seidl