John Fluke Mfg. Co., Inc.

National Instruments Corporation

Kasi S Bhaskar

James K Peckol

Alden J Carlson

Marshall H Scott

Dennis L Lambert

Alastair N Couper

A system for programming a computer provides a set of software-based virtual machines each for instructing a computer to carry out a selected operation. Each virtual machine is represented by a virtual front panel displayed on a screen and each virtual front panel graphically displays operator controllable values of input and output parameters utilized by the virtual machine it represents. The system is adapted to synthesize a new virtual machine for instructing the computer to perform a sequence of operations wherein each operation is carried out by the computer according to the instructions of an operator selected one of the existing virtual machines. The system also creates a new virtual front panel for displaying input and output parameters associated with the new virtual machine. The system permits the operator to program the computer by directing synthesis of a hierarchy of virtual machines.

Virtual machine programming system

A method of manufacturing a circuit board from a copper clad board comprises the steps of designing a circuit configuration of the circuit board on a computer-aided design system and then determining a desired circuit configuration outline on the computer-aided design system from the circuit configuration. The desired circuit configuration outline is provided to a computer-aided machining system which controls a laser, milling machine and the like to remove conductive material along the outline, leaving conductive material formed adjacent the removed material as the circuit configuration.

Computer-produced circuit board

A test system for functionally testing and troubleshooting microprocessor-based systems and assemblies is disclosed wherein the test system is connected in place of the microprocessor circuit of the unit being tested (UUT). The test system is itself a microprocessor-based system and includes a microprocessor circuit which is supplied with the UUT clock signal and is the same type of microprocessor circuit as is utilized by the UUT. The test system periodically switches this microprocessor into signal communication with the UUT for a single UUT bus cycle to perform UUT read or write operations. During remaining time periods, the test system microprocessor circuit is in signal communication with the remaining portion of the test system to analyze data obtained from the UUT bus during the previous UUT write or read operation and to establish the signals to be used in the next UUT write or read operation. Various test sequences are provided for testing the UUT bus, RAM, ROM, and write-responsive I/O registers. In addition, a mode of operation is provided wherein the test system interrogates a fully functional assembly of the type to be tested to derive a memory map and test parameters that permit the test system to perform RAM, ROM, and I/O tests without prior knowledge of the UUT operational sequence or allocation of address space. A test probe provides a visual indication that the logic level at a monitored circuit node is high, low, invalid, or is a sequence of pulses of all three logic levels. The test probe also provides for injection of logical high pulses, logical low pulses or an alternating pulse sequence of high and low pulses. Probe logic level detection and pulse injection can be asynchronous or can be selectively synchronized so that logic level detection or pulse injection occurs with each UUT write or read operation.

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Seattle, WA, United States of America

Kasi S Bhaskar