Cirrus Logic Inc.

Kartik Nanda

John L Melanson

Aryesh Amar

Bruce Eliot Duewer

Timothy Thomas Rueger

Jerome E Johnston

Dan Bernard Kasha

Rahul Singh

John James Paulos

Karl Ernesto Thompson

Larry L Harris

Mauro L Gaetano

Thirumalai Rengachari

Giri N Rangan

Amiya Anand Chokhawala

Saibun Wong

A power supply system and method includes a switch state controller that is operational to control a switching power converter during certain power loss conditions that cause conventional switch state controllers to have diminished or no functionality. In at least one embodiment, during certain power loss conditions, such as when an auxiliary power supply is in standby mode or when the switching power converter is not operating, a power supply for the switch state controller does not provide sufficient operating power to the switch state controller during certain power loss conditions. In at least one embodiment, during such power loss conditions power is generated for the switch state controller using sense input and/or sense output currents of the switching power converter to allow an integrated circuit (IC) switch state controller to generate a control signal to control a switch of the switching power converter.

Switch state controller with a sense current generated operating voltage

A power control system includes a delta sigma modulator to generate output values for use in controlling a switching power converter. In at least one embodiment, the delta sigma modulator includes two ranges of available output values and a range of one or more unavailable intermediate output values, wherein the range of one or more unavailable intermediate output values represent a gap in available output values. Each unavailable intermediate output value represents an output value that is not generated by the delta sigma modulator. In at least one embodiment, the delta sigma modulator includes a quantizer output remapping module that remaps quantizer output values within the range of one or more unavailable intermediate output values of the delta sigma modulator to new output values within one of the ranges of available output values.

Delta sigma modulator with unavailable output values

A temperature and process-stable magnetic field sensor bias current source provides improved performance in Hall effect sensor circuits. A switched-capacitor sensing element is used to sense either a reference current or the bias current directly. A current mirror may be used to generate the bias current from the reference current, and may include multiple current source transistors coupled through corresponding control transistors that are switched using a barrel shifter to reduce variations in the bias current due to process variation. The current mirror control may be provided via a chopper amplifier to reduce flicker noise and the current mirror control voltage may be held using a track/hold circuit during transitions of the chopper amplifier to further reduce noise due to the chopping action.

Temperature and process-stable magnetic field sensor bias current source

Mode selection circuitry selects one of a plurality of operational modes supported by an integrated circuit by detecting a selected connection between a first terminal of the integrated circuit and a mode control terminal of the integrated circuit. Other including a mode control terminal coupled to an integrated circuit for receiving a mode selection signal and mode select circuitry for selecting an operational mode of the integrated circuit in response to a frequency of the mode control signal.

Circuits and methods for implementing mode selection in multiple-mode integrated circuits

A system for determining a data converter clock operating mode includes measurement circuitry which measures a master clock frequency of a master clock signal and a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency, the frequency ratio, and a characteristic of an additional data clock signal to an operating mode of the data converter. In another embodiment, the mapping system maps measurements of the master clock frequency alone to a data converter operating mode. In a further embodiment, the measurement circuitry measures the master clock frequency of a master clock signal, which is received directly from a master clock signal source without a modification in the master clock frequency.

Systems and methods for clock mode determination utilizing master clock frequency measurements

A system-on-chip (SoC) integrated circuit including an interleaved delta-sigma analog to digital converter (ADC) provides for reduced noise in the ADC conversions. The ADC is operated intermittently and the balance of the digital circuits forming the system are halted while the conversions take place. The halted portion of the system may include an output low-pass filter of the ADC. The system may include a processor core or other logic having a clock frequency unrelated to the ADC modulator clock frequency that is not otherwise clock-managed to reduce noise induced in the converter output by the operation of the core or other logic.

System-on-chip (SoC) integrated circuit including interleaved delta-sigma analog-to-digital converter (ADC)

A delta-sigma analog to digital converter (ADC) having an intermittent power down state between conversion cycles provides for power consumption savings when the converter is in a lower sample rate operating mode. Clocks provided to the digital portions of the converter are disabled, except for a periodic interval in which a conversion is performed at the higher selectable sample rate of the converter. The analog portions of the converter can also be disabled, but are re-enabled for a predetermined time period and reset before the digital clocks are enabled, so that the loop filter and feedback value supplied from the quantizer to the loop filter are stable prior to each conversion.

Delta-sigma analog-to-digital converter (ADC) having an intermittent power-down state between conversion cycles

A system for determining a data converter operating mode includes measurement circuitry that measures a master clock frequency of a master clock signal received without a modification in frequency from a master clock signal source and that measures a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter. In other embodiments, mapping systems map the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter based on mode priority constraints. In additional embodiments, mapping systems map the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter by narrowing the choices of master clock divide ratios and subsequently determining an operating mode from the frequency ratio.

Systems and methods for clock mode determination utilizing prioritization criteria

A method of interfacing circuits operating in different voltage domains includes receiving a first signal with a first circuit operating in a first voltage domain and generating a second signal with a second circuit operating in a second voltage domain. The second signal is level shifted between the first and second voltage domains with a level shifter and synchronized with the first signal with a third circuit operating in the first voltage domain.

Circuits and methods for reducing the effects of level shifter delays in systems operating in multiple voltage domains

A delta-sigma having quantizer code pattern detection controlled dither reduces the probability of 'stuck' code sequences that occur when the input signal and feedback signal are equal and thus no quantizer output change occurs. In particular, in modulators that are periodically reset, the pattern detection and dither control reduce the probability of a stuck code sequence at startup. A pattern detection circuit detects a sequence of unchanging quantizer output values and injects a signal at the quantizer input to cause the quantizer to change levels. The injected signal may be a dither signal that is increased in amplitude in response to the detection of unchanging code sequences and then decreased when the quantizer output changes.

Delta-sigma modulator having quantizer code pattern detection controlled dither

A system for determining a data converter operating mode includes measurement circuitry for measuring master clock frequency of a master clock signal and a frequency ratio between a frequency of a data clock signal and the master clock frequency and a mapping system for mapping the measurement of the frequency ratio to an operating mode of the data converter. The mapping system generates a set of candidate divide ratios for dividing the master clock frequency to generate corresponding internal master clock frequencies of an internal clock signal and determines the lowest divide ratio which generates a supported internal master clock frequency. In an alternate embodiment, the mapping system determines the divide ratio required by a filter of the data converter by dividing the data clock to master clock frequency ratio by a data clock to internal clock frequency ratio between the data clock frequency and the frequency of an internal clock signal. In additional embodiments, the mapping system gives preference to natural number divide ratios during mode mapping.

Systems and methods for clock mode determination utilizing divide ratio testing

A method of determining an internal operating mode of an electronic circuit derives multiple comparison rates from a rate of a master clock input, computes one or more clock ratios of the comparison rates to a rate of a sample rate clock input, and determines whether any of the clock ratios is a valid ratio representing a supported clock configuration. The appropriate internal operating mode is then selected based on the valid ratio. In the illustrative embodiment, a clock autodetect unit uses two trip frequencies to derive at least first and second clock comparison rates. The audio converter can operate in three distinct modes (base, high and quad modes). The base mode is selected when the clock ratio is about 256, the high mode is selected when the clock ratio is about 128, and the quad mode is selected when the clock ratio is about 64. A multiplexer can be used to sequence through the computer clock ratios to ensure that a highest valid ratio is used among a plurality of valid ratios.

Scheme for determining internal mode using MCLK frequency autodetect

A method of exchanging data through a serial port includes transmitting data as an output stream of frames defined by edges of a frame clock signal, a first data bit of a current frame transmitted during a time period starting in a preceding frame and extending after an edge of the frame clock signal defining the start of the current frame.

Circuits and methods for exchanging data through a serial port and systems using the same

Techniques related to a digital filter include at least one decimator disposed between an integrator section and a comb section such that the transfer function of the filter has split zeros. The resulting filter implementation employs considerable less silicon real estate than other prior art implementations with spread zeros, and has more design flexibility with improved resulting performance than the Hogenauer implementation.

Techniques for spreading zeros in a digital filter with minimal use of registers

A method and system for selecting implementation of a filter controller between a single conversion that ensures a fully-settled converted output and a continuous conversion of an input signal are disclosed. State machine determines whether convert start signal has a duration, which ends on or before a first occurrence of a conversion done on the input signal. Conversion done is an occurrence of when a bit set has been converted from the input signal. If convert start signal has a duration which ends on or before the first occurrence of conversion done, then state machine selects and implements single conversion of the input signal. Digital system ensures a fully-settled converted output by waiting for the filter to receive and filter a predetermined number of bit sets for a conversion output and then outputting the conversion output. Otherwise, state machine selects and implements continuous conversion of the input signal.

Method and system for selecting implementation of a filter controller between a single conversion mode that ensures a fully-settled converted output and a continuous conversion mode

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Austin, TX, United States of America

Kartik Nanda