Nvidia Corporation

Kartik Joshi

Tezaswi Raja

Sachin Satish Idgunji

Gunaseelan Ponnuvel

Abhishek B Akkur

Wen Yueh

Siddharth Saxena

Chad Plummer

Krishnamraju Kurra

Ben Faulkner

Vinayak Bhargav Srinath

Divyesh Shah

Andy Chamas

In-chip decoupling capacitor circuits refer to decoupling capacitors (DCAPs) that are placed on a chip. These DCAPs are generally used to manage power supply noise for the chip, and can be utilized individually or as a distributed system. In some cases, DCAPs may make up a significant portion of the chip. Unfortunately, defects in DCAPs will degrade over time, will encroach into active logic, and will further cause automatic test pattern generation (ATPG) failure. To date, there has been a lack of structural test coverage for DCAP circuits, which reduces test coverage of the chip as a whole. To this end, defects on the chip as they relate to DCAPs (i.e. shorts in the DCAP) may not be detected. The present disclosure provides a structural test system and method for DCAPs and other passive logic components located on-chip.

Testing system and method for in chip decoupling capacitor circuits

Introduced herein is an improved technique of recovering system frequency margin via distributed CPMs. The introduced technique creates and distributes multiple sets of always sensitized critical path replicas across a chip and monitors them for timing failure. The introduced technique takes feedback from these critical path replicas and dynamically boosts the clock frequency of the chip to remove the margin. The introduced technique provides more accurate and more comprehensive coverage of a chip performance.

System frequency margin recovery via distributed critical path monitors (CPM)

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Santa Clara, CA, United States of America

Kartik Joshi