Qualcomm Incorporated

Kartik Gunvantbhai Desai

Darshan Kumar Nandanwar

Hithesh Hassan Lepaksha

Sagar Bamashetti

Raghava Rao Mv

Raghava Rao M V

This disclosure provides systems, methods, and devices for memory systems that support SRAM fault correction. In a first aspect, a method includes receiving, by a memory controller coupled to a memory module through a first channel and configured to store data in and access data stored in the memory module through the first channel from a host device, data to be stored in a memory of the memory module, determining, by the memory controller, a row in the memory at which the data will be stored, determining, by the memory controller based on the row, an address associated with the row, wherein the address indicates one bit location in the row at which data will not be stored, and storing, by the memory controller, the data at the row in accordance with the address, wherein the data is not stored at the one bit location.

Static random access memory (SRAM) fault correction

A method includes executing a first pointer authentication instruction, including a first pointer authentication code, on a pointer in a speculative path of a pipeline. The method also includes determining whether the first pointer authentication code for the pointer fails. The method further includes determining whether the first pointer authentication code for the pointer differs from a previous pointer authentication code for the pointer in response to the first pointer authentication code failing. The method still further includes incrementing a failure counter in response to determining that the first pointer authentication code for the pointer failed and that the first pointer authentication code for the pointer differs from the previous pointer authentication code for the pointer. The method additionally includes determining whether the failure counter is greater than a threshold value and performing a defensive action in response to the failure counter being greater than the threshold value.

Systems and methods for defending against side channel attacks to speculative execution of processor pipeline instructions

Optimizing cache energy consumption in processor-based devices is disclosed herein. In some aspects, a processor-based device comprises a way lookup table (WLUT) circuit that is configured to receive an effective address (EA) for a memory access request. The WLUT circuit determines that a tag portion of the EA corresponds to a tag of a WLUT entry among a plurality of WLUT entries. In response, the WLUT circuit transmits a predicted way indicator of the WLUT entry to a cache controller. The cache controller accesses, in a set among a plurality of sets of a cache memory device corresponding to a set portion of the EA, only a predicted tag way among a plurality of tag ways of the cache memory device indicated by the predicted way indicator and only a predicted data way among a plurality of data ways of the cache memory device indicated by the predicted way indicator.

Optimizing cache energy consumption in processor-based devices

A system for performing predictive run-time thermal mitigation in a processor uses at least a first temperature sensor and a first power sensor or meter to measure a junction temperature, T, value and power consumption, P, value in the processor and predicts what a temperature, TEMP, value of the processor will be in a later clock cycle of the processor based at least in part on the Tand Pvalues. If the TEMPvalue exceeds a preselected temperature threshold, TH, value, one or more thermal mitigation actions are taken to ensure that a future Tvalue measured n sample periods from the current sample period k of the processor will not exceed the THvalue.

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Savarkundla, India

Kartik Gunvantbhai Desai