Intel Corporation

Micron Technology Incorporated

Karthikeyan Ramamurthi

Aliasgar S Madraswala

Daniel R Elmhurst

Robert Melcher

Quan H Ngo

Purval Shyam Sule

Pranav Kalavade

Bharat M Pathak

Binh N Ngo

Naveen Prabhu Vittal Prabhu

Sreeram Krishnamachari

Some embodiments include apparatuses and methods using memory cells and a control unit to suspend an erase operation performed on a first portion of the memory cells and to suspend a program operation performed on a second portion of the memory cells while the erase operation is suspended. The control unit includes register circuitry to store status information indicating that the program operation is suspended while the erase operation is suspended.

Memory device including concurrent suspend states for different operations

A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.

System and method for performing a concurrent multiple page read of a memory array

An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.

High bandwidth datapath load and test of multi-level memory cells

A flash memory includes multi-level cells (MLC) that are programmed with a combination of coarse gate voltage steps and fine gate voltage steps. The multi-level cells include floating gate transistors that are programmed by modifying the threshold voltages of the floating gate transistors. Coarse gate voltage steps are used until the threshold voltage any of the transistors being programmed reaches a reference value, and fine steps are used thereafter.

Flash memory with coarse/fine gate step programming

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Folsom, CA, United States of America

Karthikeyan Ramamurthi