Texas Instruments Corporation

Karthikeyan Gunasekaran

Eeshan Miglani

Jagannathan Venkataraman

Shagun Dusad

Rahul Anand Sharma

Santhosh Kumar Gowdhaman

Jaiganesh Balakrishnan

Visvesvaraya Appala Pentakota

Sandeep Kesrimal Oswal

Sarma Sundareswara Gunturi

Sthanunathan Ramakrishnan

Nagarajan Viswanathan

Ram Narayan Krishna Nama Mony

Rakesh Chikkanayakanahalli Manjunath

Sarma Sudareswara Gunturi

Shalu Francis

Aswath V S

Snehasish Roychowdhury

An example apparatus includes quantization feedback circuitry (QFC) including an input terminal coupled to an output terminal of voltage-controlled oscillator (VCO) circuitry and an input terminal coupled to an output terminal of first frequency divider circuitry (FDC). The example apparatus also includes second FDC including an output terminal coupled to an input terminal of phase frequency detector (PFD) circuitry and an input terminal coupled to an output terminal of the first FDC. Also, the example apparatus includes masking logic circuitry including an output terminal coupled to an input terminal of the QFC, an input terminal coupled to the output terminal of the VCO circuitry, and an input terminal coupled to the output terminal of the second FDC. The example apparatus also includes adder circuitry including an input terminal coupled to an output terminal of the PFD circuitry and an input terminal coupled to an output terminal of the QFC.

Quantization extraction for phase-locked loop oscillators

In an example, a system includes a phase frequency detector (PFD) coupled to a charge pump, and a loop filter coupled to the charge pump. The system also includes a voltage controlled oscillator (VCO) coupled to the loop filter. The system includes a fast Fourier transform (FFT) engine coupled to an output of the VCO, the FFT engine configured to estimate a phase and a magnitude of reference spurs of an input reference signal. The system includes spur correction circuitry coupled to an input of the VCO, the spur correction circuitry configured to correct for the reference spurs of the input reference signal based at least in part on the phase and magnitude of the reference spurs.

Charge pump spur correction

A spur correction system for a transmit chain having an interleaving multiplexer. In some embodiments, the spur correction system includes a spur sense chain, a correction controller, and a Q path corrector. The interleaving multiplexer combines signals from multiple bands in response to a clock signal. The spur sense chain estimates an error that is in phase with the clock signal (an I-phase error) and an error that is a derivative of the clock signal (a Q-phase error). The correction controller compensates for the estimated I-phase error by injecting an I-phase correction signal into the transmit chain. The Q path corrector compensates for the estimated Q-phase error by selectively connecting one or more capacitors within the interleaving multiplexer.

F/2 spur estimation and correction

A radio frequency transmitter includes an upconverter that outputs in-phase (I) and quadrature (Q) signals, a digital timing offset circuit, first and second digital-to-analog converters (DACs), an analog timing offset removal circuit, first and second pulse shapers, and an adder. The digital timing offset circuit introduces a time offset between the I and Q signals. The first and second DACs output analog I and Q signals, respectively, and have first and second clock signals, respectively. The first and second clock signals have the same frequency and are offset relative to each other by the time offset. The analog timing offset removal circuit removes the time offset between the analog I and Q signals. The first and second pulse shapers receive the analog I and Q signals, respectively, and output pulse-shaped I and Q signals. The adder receives the pulse-shaped I and Q signals and outputs an intermediate frequency signal.

Low intermediate frequency transmitter

A circuit includes first and second operational amplifiers, each including positive and negative inputs and first and second internal nodes. A mixer couples first and second input nodes to the positive and negative inputs of the operational amplifiers. The mixer switches the first and second input nodes between the positive and negative inputs of the first and second operational amplifiers in accordance with clock signals. A first cancellation capacitor couples to the first input node, and a second cancellation capacitor couple to the second input node. First and second switches selectively couple the first cancellation capacitor to the first and second internal nodes, respectively, of the first operational amplifier. Third and fourth switches selectively couple the second cancellation capacitor to the first and second internal nodes, respectively, of the second operational amplifier.

Cancellation capacitor for aliasing and distortion improvement

A digital-to-analog converter includes an adder having a plurality of inputs and an output coupled to the output of the converter. The converter further includes a plurality of digital-to-analog (DAC) elements, each DAC element has an output coupled to an input of the adder, and each DAC element has a DAC element input. A plurality of comparators have outputs coupled to a DAC element input. A first input of each comparator is coupled to the input of the converter. A second input of each comparator is selectively coupled to one of a predetermined voltage and a pseudo-random bit sequence (PRBS[n]).

Digital-to-analog converter and method of operating

This disclosure includes an analog-to-digital converter (ADC) including multiple digital-to-analog converter (DAC) elements and multiple comparators, with an output of each of the comparators provided to an input of a different one of the multiple DAC elements. The ADC also includes a first voltage connection provided to each of the multiple comparators and multiple second voltage connections, with a different second voltage connection provided to each of the multiple comparators. The ADC further includes first and second resistor ladders, with the first resistor ladder configured to be switchably coupled to a first voltage supply and the second resistor ladder configured to be switchably coupled to a second voltage supply. Each of the second voltage connections is configured to be switchably coupled to a different one of the nodes in the first resistor ladder and to a different one of the nodes in the second resistor ladder.

High-speed dynamic element matching

The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.

Delta sigma modulator with dynamic error cancellation

The disclosure provides a delta sigma modulator. The delta sigma modulator includes a summer. The summer generates an error signal in response to an input signal and a feedback signal. A loop filter is coupled to the summer and generates a filtered signal in response to the error signal. A quantizer is coupled to the loop filter and generates a quantized output signal in response to the filtered signal. A digital to analog converter (DAC) is coupled to the summer, and generates the feedback signal in response to a plurality of selection signals. A modified data weighted averaging (DWA) block is coupled between the quantizer and the DAC. The modified DWA block receives a clock signal and generates the plurality of selection signals in response to the quantized output signal and a primary coefficient. The primary coefficient varies with the clock signal.

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Chennai, India

Karthikeyan Gunasekaran