International Business Machines Corporation

Karthik Yogendra

Dimitri Houssameddine

Heng Wu

Saba Zare

Robert Russell Robison

Eric Raymond Evarts

Kangguo Cheng

Ruilong Xie

Chih-Chao Yang

Daniel C Edelstein

Julien Frougier

Praneet Adusumilli

Eugene John O'Sullivan

Hiroyuki Miyazoe

Ashim Dutta

John Christopher Arnold

Nathan P Marchack

Ardasheir Rahman

Adra Carr

HsinYu Tsai

A semiconductor device including a magnetic tunnel junction (MTJ) stack, a first metal line above the MTJ stack and a magnetoelectric material layer above the first metal line. A semiconductor device including an array of magnetic tunnel junction (MTJ) stacks, a first metal line connected physically and electrically to a top electrode of each MTJ stack in a row of the array of MTJ stacks and a magnetoelectric material layer above the first metal line, connected physically and electrically to the first metal line. A method including forming an array of magnetic tunnel junction (MTJ) stacks, forming a first metal line above a row of the array of MTJ stacks, and forming a magnetoelectric material layer above the first metal line, connected physically and electrically to the first metal line.

Magnetic tunnel junction device with magnetoelectric assist

A memory device with in-array magnetic shield includes an electrically conductive structure embedded within an interconnect dielectric material located above a first metal layer. The electrically conductive structure includes a bottom electrode. The memory device further includes a magnetic tunnel junction stack located above the bottom electrode, a dielectric filling layer surrounding the magnetic tunnel junction stack, one or more connecting vias extending through the dielectric filling layer and the interconnect dielectric material until a top portion of the first metal layer, and one or more dummy vias located between the one or more connecting vias and the magnetic tunnel junction stack for conducting an external magnetic field around the memory device.

In-array magnetic shield for spin-transfer torque magneto-resistive random access memory

An approach for minimizing stack height and reducing resistance of an MRAM (Magnetoresistive random-access memory) is disclosed. The approach leverages an MRAM device with a T shape magnetic bottom electrode. The T shape magnetic bottom electrode can be made from a lower resistance metal such as cobalt. Furthermore, the method of creating the MRAM can include, depositing a low-k dielectric layer, forming bottom electrode via within the low-k dielectric layer, depositing bottom electrode metal liner on the bottom electrode via, depositing bottom electrode magnetic metal on the bottom electrode metal liner, planarizing the bottom electrode magnetic metal, depositing coupling layer and an MRAM stack on the bottom electrode magnetic metal, patterning and etching anisotropically the MRAM stack and depositing in-situ conformal dielectric layer and forming a top contact via on the MRAM stack.

Compact MRAM architecture with magnetic bottom electrode

A device includes a Magnetic Tunnel Junction (MTJ) memory element comprising, a reference layer, a free layer, and a magnetic tunneling layer between the reference layer and the free layer; and a pair of magneto-electric controlling layers, which have in-plane uniaxial anisotropy, wherein the pair of magneto-electric controlling layers are disposed below the free layer.

Magneto-electric low power analogue magnetic tunnel junction memory

A memory system may include a magnetic tunnel junction stack, a first high resistance tunnel barrier, and a first voltage controlled magnetic anisotropy write layer. The first voltage controlled magnetic anisotropy write layer may be adjacent the high resistance tunnel barrier, and the voltage controlled magnetic anisotropy write line may include a magnetic material in direct contact with a high resistance tunnel barrier.

Low power MTJ-based analog memory device

Provided is a magnetoresistive random-access memory (MRAM) cell. The MRAM cell comprises a first heavy metal layer and a first magnetic tunnel junctions (MTJ) coupled to the first heavy metal layer. The first MTJ has a first area. The MRAM cell further comprises a second MTJ. The second MTJ is connected in series with the first MTJ, and the second MTJ has a second area that is different than the first area. The second MTJ shared a reference layer with the first MTJ. The MRAM cell further comprises a second heavy metal layer that is coupled to the second MTJ.

Two-bit magnetoresistive random-access memory cell

A method for forming an in-situ drift-mitigation liner on a sidewall of a phase-change material (PCM) device stack includes providing an intermediate device including a substrate including a bottom wiring portion, a bottom electrode metal layer, a drift-mitigation liner layer, an active area layer, a carbon layer, a top electrode metal layer, patterning the top electrode metal layer to form a top electrode, performing a first intermediate angle ion beam etch (IBE), etching the carbon layer and the active area layer, which are formed on the drift-mitigation liner, to form a carbon portion and an active area portion of the PCM device stack, and performing a low angle IBE, etching the drift-mitigation liner and redepositing material etched from the drift-mitigation liner as a conductive liner material on sidewalls of the PCM device stack including exposed portions of the carbon portion, the active area portion, and the top electrode.

In-situ drift-mitigation liner for pillar cell PCM

A method of manufacturing a double magnetic tunnel junction device is provided. The method includes forming a first free layer, forming a first tunnel barrier layer on the free layer, forming a reference layer on the first tunnel barrier layer, forming a second tunnel barrier layer on the reference layer, and forming a second free layer on the second tunnel barrier layer. An area of the second free layer is less than an area of the first free layer. Also, the first free layer, the first tunnel barrier layer and the reference layer are a first magnetic tunnel junction, and the reference layer, the second tunnel barrier layer and the second free layer are a second magnetic tunnel junction.

Magnetoresistive random-access memory device including magnetic tunnel junctions

Semiconductor devices and methods of forming the same include forming a dummy gate on a stack of alternating channel layers and sacrificial layers. A spacer layer is formed over the dummy gate and the stack. Portions of the spacer layer on horizontal surfaces of the stack are etched away to form vertical spacers. Exposed portions of the stack are etched away. Semiconductor material is grown from exposed sidewalls of remaining channel layers to form source and drain structures that are constrained in lateral dimensions by the vertical spacers.

Spacer-confined epitaxial growth

MRAM devices with in-situ encapsulation are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cell stacks, wherein the MRAM stack includes a bottom electrode, a MTJ, and a top electrode, and wherein the patterning is performed using an intermediate angle IBE landing on the dielectric; removing redeposited metal from the memory cell stacks using a high angle IBE; redepositing the dielectric along the sidewalls of the memory cell stacks using a low angle IBE to form a first layer of dielectric encapsulating the memory cell stacks; and depositing a second layer of dielectric, wherein the first/second layers of dielectric form a bilayer dielectric spacer structure, wherein the patterning, removing of the redeposited metal, and redepositing the dielectric steps are all performed in-situ. An MRAM device is also provided.

MRAM device formation with in-situ encapsulation

A method of forming a semiconductor structure includes forming a first spacer material over two or more mandrels disposed over a magnetoresistive random-access memory (MRAM) stack. The method also includes performing a first sidewall image transfer of the two or more mandrels to form a first set of fins of the first spacer material over the MRAM stack, and performing a second sidewall image transfer to form a plurality of pillars of the first spacer material over the MRAM stack. The pillars of the first spacer material form top electrodes for a plurality of MRAM cells patterned from the MRAM stack.

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Karthik Yogendra