Texas Instruments Corporation

Karthik Vasanth

Richard Gene Burch

Sharad Saxena

Joseph C Davis

Purnendu K Mozumder

Suraj Rao

Chenjing L Fernando

Mahalingam Nandakumar

Ih-Chin Chen

E Ajith Amerasekera

Suribhotla Rajasekhar

Ismail Hakki Oguzman

Arash Loloee

Pushkar Prabhakar Apte

Shian-Wei Aur

An ultrasound transmitter including intrinsic output zeroing is disclosed herein. A transmitter for generating ultrasound signals includes a first transmitter output driver and a first transmitter input driver. The first transmitter output driver includes an N-type device serially coupled to a P-type device. The first transmitter input driver includes an N-type device serially coupled to a P-type device. An output of the first transmitter input driver is coupled to an input of the first transmitter output driver. The first transmitter output driver drives an output of the transmitter to a first voltage and the first transmitter input driver drives the output of the transmitter to a second voltage while the first transmitter output driver is disabled.

High voltage ultrasound transmitter with gate protection diodes and intrinsic output zeroing

A field effect transistor with a dual-counterdoped channel is disclosed. The transistor features a channel comprising a first doped region () and a second doped region () underlying the first doped region. A source and drain () are formed adjacent to the channel. In one embodiment of the present invention, the first doped region () is doped with arsenic, while the second doped region () is doped with phosphorus. The high charge-carrier mobility of the subsurface channel layer () allowing a lower channel dopant concentration to be used, which in turn allows lower source/drain pocket doping. This reduces the capacitance and response time of the transistor.

Dual-counterdoped channel field effect transistor and method

An operational lifetime, and also performance characteristics, can be accurately predicted for an experimental transistor design ( ) and a specified set of fabrication process conditions ( ), without actually fabricating and testing a physical transistor made according to the particular design data and process conditions. With respect to the prediction of an operational lifetime, the operational lifetime can be expressed as a function of the size of a gate overlap ( ) of the transistor, and this relationship is valid throughout a selected semiconductor technology for which the transistor is designed. The size of the gate overlap is determined by selecting a combinations of values for two process conditions.

Method and apparatus for predicting an operational lifetime of a transistor

Integration of dual voltages on a single chip can be accomplished with a minimum of extra masks by optimizing only the MDD implant of the peripheral transistors, while other implants remain the same for both transistor types. This meets lifetime specifications without unnecessary expense.

Integrating dual supply voltages using a single extra mask level

A method and system for providing optimal tuning for complex simulators. The method and system include initially building at least one RSM model having input and output terminals. Then there is provided a simulation-free optimization function by constructing an objective function from the outputs at the output terminals of the at least one RSM model and experimental data. The objective function is optimized in an optimizer and the optimized objective function is fed to the input terminal of the RSM. Building of at least one RSM model includes establishing a range for the simulation, running a simulation experiment for the designed experiment, extracting relevant data from said experiment and building the RSM model from the extracted relevant data. The step of running a simulation experiment comprises the step of running a DOE/Opt operation. The objective function is, for example, the square root of the sum of the squares at all of the differences between the target values and the observed values at all points being investigated. The optimizing in the optimizer is preferably a gain function which adjusts the parameters to the input based upon the error signal to minimize the error signal.

Method and system for using response-surface methodologies to determine optimal tuning parameters for complex simulators

Method for adequately modeling process induced variabilities is disclosed that comprises the steps of acquiring experimental data and defining a particular design space. Values for the mean and standard deviation of the experimental data at each of the points defining the design space are calculated. The experimental values of the output parameters at each of the design points is normalized to extract the shape of the distribution of each of the design points. The normalized values are then merged to form a cumulative distribution function associated with the data. The cumulative distribution function is applied to a new design point in a predicted fashion by first calculating a mean and standard deviation value for the new point by interpolating from the mean and standard deviation values from the experimental data. The cumulative distribution function is then scaled and centered using the interpolated mean and standard deviation values to provide a predicted data distribution for the new design point.

System and method for non-parametric modeling of processed induced variability

A statistical design method is provided for minimizing the impact of manufacturing variations on semiconductor manufacturing by statistical design which seeks to reduce the impact of variability on device behavior. The method is based upon a Markov representation of a process flow which captures the sequential and stochastic nature of semiconductor manufacturing and enables the separation of device and process models, statistical modeling of process modules from observable wafer states and approximations for statistical optimization over large design spaces. The statistical estimation component of this method results in extremely accurate predictions of the variability of transistor performance for all of the fabricated flows. Statistical optimization results in devices that achieve all transistor performance and reliability goals and reduces the variability of key transistor performances.

Design of microelectronic process flows for manufacturability and performance

The invention comprises a method of determining the thermal straggle of microelectronic devices having a pocket dopant implant that is formed under substantially the same doping conditions. The method comprises measuring the operating characteristics of each device (,) and obtaining a one-dimensional doping profile of dopant ions in the devices (,). A total lateral straggle of the dopant ions in the devices is determined in response to the operating characteristics and the one-dimensional doping profile of the dopant ions (,). An as-implanted straggle of the dopant ions in the devices is determined in response to the doping conditions (,). A thermal straggle of the dopant ions is calculated utilizing the as-implanted straggle and the total lateral straggle (,).

Method of pocket implant modeling for a CMOS process

A dual voltage chip is fabricated with no intermediate-doped (LDD or MDD) area in the high-voltage transistors by adjusting the gate sidewall spacer thickness and the source/drain implant.

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Richardson, TX, United States of America

Karthik Vasanth