Intel Corporation

Karthik Vaithianathan

Sridhar Lakshmanamurthy

Gary J Lavelle

Atul Kwatra

Dharmin Y Parikh

In some embodiments a memory controller is disclosed that includes at least one command/address input buffer to receive commands and addresses. The addresses specify a memory bank and a location within the memory bank. An arbiter, coupled to the at least one command/address input buffer, merges commands and addresses from the at least one command/address input buffer and sorts the commands and addresses based on the addresses specified. A plurality of bank buffers, coupled to the arbiter and associated with memory banks, receive commands and addresses for their associated memory banks. A scheduler, coupled to the plurality of bank buffers, groups commands and addresses based on an examination of at least one command and address from the bank buffers. Other embodiments are otherwise disclosed herein.

Memory controller with bank sorting and scheduling

During high performance renormalization for video encoding, renormalization may involve detecting a leading number of '0's in a range value of an input stream of symbols, a run of '1's in an offset value of the input stream of symbols, and a run of &#x2018;0&#x2019;s following the run of &#x2018;1&#x2019;in the offset value. A bitstream may be outputted based on an iteration window for a number of renormalization iterations. The iteration window may comprise a bit range after the run of &#x2018;1&#x2019;s in the offset value, and the number of renormalization iterations may be based on the leading number of &#x2018;0&#x2019;s in the range value. A run of &#x2018;1&#x2019;s followed by one or more &#x2018;0&#x2019;s may be identified as a particular pattern.

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Chandler, AZ, United States of America

Karthik Vaithianathan