Intel Corporation

Karthik Vaidyanathan

Prasoonkumar Surti

Abhishek R Appu

Joydeep Ray

Carsten Benthin

Murali Ramadoss

Michael Apodaca

Abhishek Venkatesh

Travis T Schluessler

Gabor Liktor

John H Feit

Altug Koker

Adam T Lake

Jonathan Kennedy

Sven Woop

Atsuo Kuwahara

Balaji Vembu

Subramaniam M Maiyuran

Jeffery S Boles

Devan Burke

Hugues Labbe

Narayan Srinivasa

Kamal Sinha

Justin E Gottschlich

Feng Chen

Eriko Nurvitadhi

Linda L Hurd

Sara S Baghsorkhi

Ben J Ashbaugh

Nicolas C Galoppo Von Borries

Rajkishore Barik

Dukhwan Kim

Nadathur Rajagopalan Satish

Tsung-Han Lin

Wenyin Fu

Josh B Mastronarde

Scott R Janus

Nikos Kaburlasos

Jacek Kwiatkowski

Vasanth Ranganathan

Elmoustapha Ould-Ahmed-Vall

Kai Xiao

Robert M Toth

Tomer Bar-On

Tomas G Akenine-Moller

Carl Jacob Munkberg

Ankur N Shah

Jon N Hasselgren

Peter L Doyle

David Robert Baldwin

James A Valerio

Sameer Kp

Philip R Laws

Marco Salvi

Michael Doyle

Farshad Akhbari

Karol A Szerszen

Slawomir Grajewski

Thomas F Raoux

Eric G Liskay

Andrew T Lauritzen

David M Cimini

Jefferson Amstutz

Joshua D Barczak

John G Gierach

Franz Petrik Clarberg

Tomasz Janczak

Eric J Hoekstra

Carson Brownlee

Alexey Supikov

Saikat Mandal

Joshua Barczak

Sreenivas Kothandaraman

Sungye Kim

Louis Feng

Michael J Norris

Abhishek Rhisheekesan

Shashank Lakshminarayana

Sudhakar Kamma

Holger Gruen

Won-Jong Lee

Pawel Majewski

Rajasekhar Pantangi

Priyanka Ladda

Manu Mathew Thomas

Stephen Junkins

Vikranth Vemulapalli

Aaron Eliot Lefohn

Rahul P Sathe

Timothy R Bauer

Pradeep Ramani

Jiasheng Chen

Weiyu Chen

Tim Foley

Anton Kaplanyan

Valentin Fuetterling

Sameer K P

Subramanian Maiyuran

Bret G Alfieri

One embodiment provides a graphics processor including a processing resource including a register file, memory, a cache memory, and load/store/cache circuitry to process load, store, and prefetch messages from the processing resource. The circuitry includes support for an immediate address offset that will be used to adjust the address supplied for a memory access to be requested by the circuitry. Including support for the immediate address offset removes the need to execute additional instructions to adjust the address to be accessed prior to execution of the memory access instruction.

Immediate offset of load store and atomic instructions

Apparatus and method for box-box testing. For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged BVH nodes; traversal circuitry to traverse query boxes through the BVH, the traversal circuitry to read a BVH node from a top of a BVH node stack and to read a query box from a local storage or memory, the traversal circuitry further comprising: box-box testing circuitry and/or logic to compare maximum and minimum X, Y, and Z coordinates of the BVH node and the query box and to generate an overlap indication if overlap is detected for each of the X, Y, and Z dimensions; distance determination circuitry and/or logic to generate a distance value representing an extent of overlap between the BVH node and the query box; and sorting circuitry and/or logic to sort the BVH node within a set of one or more additional BVH nodes based on the distance value.

Apparatus and method for performing box queries in ray traversal hardware

For example, one embodiment of an apparatus comprises: ray traversal hardware logic to perform traversal operations to traverse rays through a bounding volume hierarchy (BVH) comprising a plurality of BVH nodes, the ray traversal hardware logic comprising a plurality of traversal storage banks to store traversal data associated with the BVH nodes and/or the rays as the ray traversal hardware logic performs the traversal operations; and a cache comprising a plurality of cache banks to store the traversal data prior to being moved into the traversal storage banks for processing by the ray traversal hardware logic; and an inter-bank interconnect comprising: a point-to-point switch matrix to couple any of the cache banks to any of the traversal storage banks; an arbiter/allocator to control the point-to-point switch matrix to establish a particular group of interconnections between the cache banks and the traversal storage banks in a given clock cycle.

Apparatus and method for routing data from ray tracing cache banks

Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.

Compression for sparse data structures utilizing mode search approximation

Joint denoising and supersampling of graphics data is described. An example of a graphics processor includes multiple processing resources, including a least a first processing resource including a pipeline to perform a supersampling operation; and the pipeline including circuitry to jointly perform denoising and supersampling of received ray tracing input data, the circuitry including first circuitry to receive input data associated with an input block for a neural network, second circuitry to perform operations associated with a feature extraction and kernel prediction network of the neural network, and third circuitry to perform operations associated with a filtering block of the neural network.

Joint denoising and supersampling of graphics data

Examples described herein relate to a manner of determining a number of bits to encode compression data. Some examples include: compressing pixel data of a region of pixels in a frame; determining a number of bits associated with at least two partitions; utilizing the determined number of bits to encode residual values generated from the compressing the pixel data; and storing the encoded residual values. In some examples, the at least two partitions comprise a first partition and a second partition. Some examples include: encoding residuals in the first partition using a number of bits associated with the first partition and encoding residuals in the second partition using a number of bits associated with the second partition. Some examples include: determining a distribution of bins of residuals, wherein each different bin represents a number of bits used to encode a residual value and determining a midpoint of a total number of residuals as a bin that stores a residual that is approximately 50 percentile of the total number of residuals of the distribution.

Memory allocation technologies for data compression and de-compression

One embodiment provides a graphics processor comprising a set of processing resources configured to perform a supersampling operation via a mixed precision convolutional neural network, the set of processing resources including circuitry configured to receive, at an input block of a neural network model, history data, velocity data, and current frame data, pre-process the history data, velocity data, and current frame data to generate pre-processed data, provide the pre-processed data to a feature extraction network of the neural network model, process the pre-processed data at the feature extraction network via one or more encoder stages and one or more decoder stages, and generate an output image via an output block of the neural network model via direct reconstruction or kernel prediction.

Temporally amortized supersampling using a mixed precision convolutional neural network

Apparatus and method for lossy displaced mesh compression. For example, one embodiment of an apparatus comprises: displacement mapping circuitry/logic to generate an original displacement-mapped mesh by performing a displacement mapping of a plurality of vertices of a base subdivision mesh; and mesh compression circuitry/logic to compress the original displacement-mapped mesh, the mesh compression circuitry/logic comprising a quantizer to quantize the displacement mapping of the plurality of vertices in view of a base mesh to generate a displacement array.

Apparatus and method for displaced mesh compression

Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

Controlling coarse pixel size from a stencil buffer

An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.

Apparatus and method for ray tracing instruction processing and execution

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

Motion biased foveated renderer

Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.

Apparatus and method for quantized convergent direction-based ray sorting

Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Compute optimization mechanism for deep neural networks

Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

Speculative execution of hit and intersection shaders on programmable ray tracing architectures

Growing community of inventors

Berkeley, CA, United States of America

Karthik Vaidyanathan