International Business Machines Corporation

Karthik V Swaminathan

Alper Buyuktosunoglu

Pradip Bose

Schuyler Eldridge

Swagath Venkataramani

Ramon Bertran Monfort

Yazhou Zu

Toshiaki Kirihata

Chen-Yong Cher

Augusto Javier Vega

Srivatsan Chellappa

Nandhini Chandramoorthy

Rajiv V Joshi

Hans Mikael Jacobson

Liang Wang

William J Song

Bulent Abali

Ankur Narang

Prashant Jayaprakash Nair

Prashant Agrawal

Doug Joseph

Embodiments for providing enhanced location-aware protection of latches in a computing environment are provided. One or more latches are combined in one or more of a plurality of bounding boxes on a two-dimensional circuit design layout based on one or more rules. A location-aware interleaving of error correction codes ('ECC') and burst error correction codes may be selectively applied to one or more latches in those of the plurality of bounding boxes, where multiple bit errors are corrected.

Location-aware protection system of latches (LAPS-L)

A system includes a determination component that determines output for successively larger neural networks of a set; and a consensus component that determines consensus between a first neural network and a second neural network of the set. A linear chain of increasingly complex neural networks trained on progressively larger inputs is utilized (e.g., increasingly complex neural networks is generally representative of increased accuracy). Outputs of progressively networks are computed until a consensus point is reached&#x2014;where two or more successive large networks yield a same inference output. At such point of consensus the larger neural network of the set reaching consensus can be deemed appropriately sized (or of sufficient complexity) for a classification task at hand.

System and method for consensus-based representation and error checking for neural networks

A computer-implemented method, a computer system and a computer program product customize generation and application of stress test conditions in a processor core. The method includes receiving a workload at the processor core, where the workload includes a plurality of instructions and the processor core comprises a plurality of macros. The method also includes obtaining macro performance data for each macro in the plurality of macros from the processor core. The method further includes determining a switching activity level for each macro in the plurality of macros when each instruction in the plurality of instructions is run based on the macro performance data. Lastly, the method includes generating a stressmark comprising the plurality of instructions in the workload, where the stressmark is associated with a macro in the plurality of macros when the switching activity level for the macro is above a minimum threshold.

Customizing stressmarks in a computer system

Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.

Determination and correction of physical circuit event related errors of a hardware design

An N modular redundancy method, system, and computer program product include a computer-implemented N modular redundancy method for neural networks, the method including selectively replicating the neural network by employing one of checker neural networks and selective N modular redundancy (N-MR) applied only to critical computations.

Reducing the cost of n modular redundancy for neural networks

A method (and structure and computer product) to optimize an operation in a Neural Network Accelerator (NNAccel) that includes a hierarchy of neural network layers as computational stages for the NNAccel and a configurable hierarchy of memory modules including one or more on-chip Static Random-Access Memory (SRAM) modules and one or more Dynamic Random-Access Memory (DRAM) modules, where each memory module is controlled by a plurality of operational parameters that are adjustable by a controller of the NNAcc. The method includes detecting bit error rates of memory modules currently being used by the NNAccel and determining, by the controller, whether the detected bit error rates are sufficient for a predetermined threshold value for an accuracy of a processing of the NNAccel. One or more operational parameters of one or more memory modules are dynamically changed by the controller to move to a higher accuracy state when the accuracy is below the predetermined threshold value.

System and method for an error-aware runtime configurable memory hierarchy for improved energy efficiency

A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.

Self-evaluating array of memory

A coarse error correction system for detecting, predicting, and correcting errors in neural networks is provided. The coarse error correction system receives a first set of statistics that are computed from values collected from a neural network during a training phase of the neural network. The coarse error correction system computes a second set of statistics based on values collected from the neural network during a run-time phase of the neural network. The coarse error correction system detects an error in the neural network during the run-time phase of the neural network by comparing the first set of statistics with the second set of statistics. The coarse error correction system increases a voltage setting to the neural network based on the detected error.

Low-overhead error prediction and preemption in deep neural network using apriori network statistics

A system and method for determining reliability-aware runtime optimal processor configuration can integrate soft and hard error data into a single metric, referred to as the balanced reliability metric (BRM), by using statistical dimensionality reduction techniques. The BRM can be used to not only adjust processor voltage to optimize overall reliability but also to adjust the number of on-cores to further optimize overall processor reliability. In some implementations, both coarse-grained actuations, based on optimal core count, and fine-grained actuations, based on optimal processor voltage (V), may be used, where feedback control can recursively re-compute soft and hard error data based on a new configuration, until convergence at an optimal configuration.

Reliability-aware runtime optimal processor configuration

Applications on different processing elements have different characteristics such as latency versus bandwidth sensitivity, memory level parallelism, different memory access patterns and the like. Interference between applications due to contention at different sources leads to different effects on performance and is quantified. A method for contention-aware resource provisioning in heterogeneous processors includes receiving stand-alone performance statistics for each processing element for a given application. Multi-core performance slowdown can be computed from the received stand-alone performance statistics. When a request to provision an application on the heterogeneous processors is received, application performance requirements of the application can be determined and a bandwidth for the application can be provisioned based on the application performance requirements and the computed multi-core performance slowdown parameter.

Contention-aware resource provisioning in heterogeneous processors

An aspect includes optimizing an application workflow. The optimizing includes characterizing the application workflow by determining at least one baseline metric related to an operational control knob of an embedded system processor. The application workflow performs a real-time computational task encountered by at least one mobile embedded system of a wirelessly connected cluster of systems supported by a server system. The optimizing of the application workflow further includes performing an optimization operation on the at least one baseline metric of the application workflow while satisfying at least one runtime constraint. An annotated workflow that is the result of performing the optimization operation is output.

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Karthik V Swaminathan