Intel Corporation

Karthik Sankaranarayanan

Willem M Beltman

Jessica Gullbrand

Eric Baugh

Stephen H Gunther

Gautham N Chinya

Harish Krishnamurthy

Krishnan Ravichandran

Helia A Naeimi

Pavan Kumar

Wayne Proefrock

Jay D Schwartz

George Matthew

Stephen J Tarsa

Sheldon Weng

Jose A Cordova

Carlos A Lopez

Disclosed embodiments relate to a prefetcher for delinquent irregular loads. In one example, a processor includes a cache memory, fetch and decode circuitry to fetch and decode instructions from a memory; and execution circuitry including a binary translator (BT) to respond to the decoded instructions by storing a plurality of decoded instructions in a BT cache, identifying a delinquent irregular load (DIRRL) among the plurality of decoded instructions, determining whether the DIRRL is prefetchable, and, if so, generating a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL.

Prefetcher for delinquent irregular loads

Methods and apparatus relating to reducing switching noise and improving transient response in voltage regulators are described. In an embodiment, one or more pulses are inserted into an output waveform of a voltage regulator. The one or more pulses introduce multiple frequencies into the output waveform of the voltage regulator (e.g., to reduce acoustic noise). In another embodiment, the output voltage of a voltage regulator is modified in response to comparison of the output voltage with at least one of a plurality of threshold values. The plurality of threshold values includes an upper trigger point voltage value and a lower trigger point voltage value. Other embodiments are also disclosed and claimed.

Techniques for reducing switching noise and improving transient response in voltage regulators

In one or more embodiments, a fixed time interval for a system is determined. The fixed time interval corresponds to time between clock ticks. A random time interval is determined based on the fixed time interval and an offset. One or more electronic components affixed to a motherboard are transitioned to a new power state when the random time interval has elapsed. By introducing a randomization to the timing element to a control signal that drives the power state transition, a periodicity for the system is disrupted. The disruption in periodicity mitigates acoustic noise generated by vibrations in electronic components and motherboards affected by current and/or voltage transitions.

Acoustic noise mitigation using periodicity disruption

Systems and methods of identifying electrical sources of audible acoustic noise may involve identifying first frequency content of a circuit board, wherein the first frequency content is associated with at least one of acoustic noise and a vibration of the circuit board. Second frequency content of an electrical signal associated with the circuit board may also be identified. In addition, a coherence between the first frequency content and the second frequency content may be determined.

Identifying electrical sources of acoustic noise

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Hillsboro, OR, United States of America

Karthik Sankaranarayanan