Inphi Corporation

Marvell Asia Pte., Ltd.

Infineon Technologies Ag

Qimonda Ag

Extreme Networks, Inc.

Other

Avaya Inc.

Karthik S Gopalakrishnan

Jamal Riani

Guojun Ren

Jorge Pernillo

Sadettin Cirit

Halil Cirit

Arun Tiruvur

Chang-Feng Loi

Belal Helal

James Lawrence Gorecki

Hamid Partovi

Luca Ravezzi

Yu Liao

Aaron W Buchwald

Roger Lapuh

Greg J Landry

Paul Unbehagen

Zenon Kuc

John Mead

Mrunmay Talegaonkar

Praveen Prabha

Junyi Sun

Parmanand Mishra

Michael Q Le

Pulkit Khandelwal

Irene Quek

Sivaraman Chokkalingam

Amber Tan

Ravindran Mohanavelu

Lawrence Tse

Srinivas Kilambi

Dirk Scheideler

Karim Vincent Abdelhalim

Edoardo Prete

Otto Schumacher

Paul Georg Lindt

Krishnan Viswanathan Iyer

Andreas Blum

Ramesh Chembeti

Niraj Singh

Satish Reddy Dhumpala

Zijun Liu

Raman Kumar Gottumukkala

Subhadeep Mukherjee

A temperature sensor system for an integrated circuit includes at least one sensor configured to generate a sensor signal indicative of a temperature in a respective location of the integrated circuit and a sensing module configured to receive the sensor signal, determine a temperature of the at least one sensor based on the sensor signal, an electrical characteristic of the at least one sensor, and a relationship between the electrical characteristic and the temperature of the at least one sensor, the relationship corresponding to variations in the electrical characteristic at a known calibration temperature, and generate a temperature signal based on the determined temperature.

Single calibration temperature based temperature sensing with differential signal generation

The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

Clock and data recovery devices with fractional-N PLL

A communication device includes an AFE configured to track and hold a first driving signal to produce a plurality of sample signals, a shift and hold module configured to store the plurality of sample signals, and an ADC configured to respectively convert the plurality of sample signals to a plurality of digitized sample signals, the ADC including a plurality of ADC slices. A DSP is configured to calibrate the AFE based on the plurality of ADC slices corresponding to the plurality of digitized sample signals and generate an output data stream comprising the plurality of digitized samples. A skew management module is configured to detect a skew of the plurality of digitized sample signals in the output data stream generated by the DSP module, generate a programmable skew offset based on the detected skew, and correct the skew in the output data stream based on the programmable skew offset.

PAM4 transceivers for high-speed communication

The present invention relates to integrated circuits. More specifically, embodiments of the present invention provide methods and systems for determining temperatures of an integrated circuit using an one-point calibration technique, where temperature is determined by a single temperature measurement and calculation using known electrical characteristics of the integrated circuit.

Voltage and temperature sensor for a serializer/deserializer communication application

The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

Embodiments generally relate to enabling configuration in networks. In one embodiment, a method includes receiving a message from an edge configuration device, wherein the message contains shortest path bridging (SPB) configuration information. The method also includes performing an intermediate system-to-intermediate system (IS-IS) configuration in response to receiving the message.

Enabling configuration in networks

Non-ideal downstream loading of a differential driver in a single ended circuit driving a communications laser&#x2014;e.g., Electro absorption Modulated Laser (EML)&#x2014;may be compensated by deploying a second matching network at the non-functional (terminated) driver output node. Certain embodiments may further compensate for distortion arising from circuit non-ideality, by introducing a laser replica downstream of the second matching network to mimic electrical properties of the laser. Embodiments may sufficiently compensate for downstream circuit non-ideality to allow replacing the bulky choke inductor of a bias tee, with a resistor. Substituting a resistor for a more complex inductor structure can simplify design and fabrication of the single-ended driver circuit, and also reduce footprint by eliminating area formerly occupied by the choke inductor. Embodiments may be particularly suited to bridge integration with other system components undergoing design migration toward double-ended modulator circuit architectures featuring a differential driver.

Configurable laser modulator driver and output matching network

Embodiments generally relate to enabling encapsulation in networks. In one embodiment, a method includes receiving a message from an edge configuration device, wherein the message contains shortest path bridging (SPB) configuration information. The method also includes performing provider backbone bridge (MAC-in-MAC) encapsulation in response to receiving the message.

Performing MAC-in-MAC encapsulation using shortest path bridging configuration information

In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.

Interleaved successive approximation register analog to digital converter

Growing community of inventors

Santa Clara, CA, United States of America

Karthik S Gopalakrishnan