Advanced Micro Devices Corporation

Ati Technologies Ulc

Karthik Rao

Indrani Paul

Sriram Sambamurthy

Dana Glenn Lewis

Wonje Choi

Wei T Huang

Joseph Lee Greathouse

Leonardo De Paula Rosa Piga

Xudong An

Donny Yi

Larry David Hewitt

Jagadish B Kotra

Shomit N Das

Anil Harwani

Oleksandr Khodorkovsky

Leonardo Piga

Aaron Joseph Grenat

Sriram Sundaram

Manish Arora

Miguel Rodriguez

Abhinav Vishnu

Mahesh Subramony

Kenneth Mitchell

A disclosed technique includes in response to a trigger to power a functional element of a device to a lower power state, operating a set of backup state elements for the functional element in a lower power mode; and resuming operation of the functional element and the backup state elements in a higher power state.

Technique for improving power state transition latency for computing device

A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.

Operating voltage adjustment for aging circuits

An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.

Low power state selection based on idle duration history

A processing unit of a processing system compiles a priority queue listing of a plurality of processor cores to run a workload based on a cost of running the workload on each of the processor cores. The cost is based on at least one of a system usage policy, characteristics of the workload, and one or more physical constraints of each processor core. The processing unit selects a processor core based on the cost to run the workload and communicates an identifier of the selected processor core to an operating system of the processing system.

Core selection based on usage policy and core constraints

In some examples, thermal aware optimization logic determines a characteristic (e.g., a workload or type) of a wavefront (e.g., multiple threads). For example, the characteristic indicates whether the wavefront is compute intensive, memory intensive, mixed, and/or another type of wavefront. The thermal aware optimization logic determines temperature information for one or more compute units (CUs) in one or more processing cores. The temperature information includes predictive thermal information indicating expected temperatures corresponding to the one or more CUs and historical thermal information indicating current or past thermal temperatures of at least a portion of a graphics processing unit (GPU). The logic selects the one or more compute units to process the plurality of threads based on the determined characteristic and the temperature information. The logic provides instructions to the selected subset of the plurality of CUs to execute the wavefront.

Apparatus and method for providing workload distribution of threads among multiple compute units

A system including a stack of two or more layers of volatile memory, such as layers of a 3D stacked DRAM memory, places data in the stack based on a temperature or a refresh rate. When a threshold is exceeded, data are moved from a first region to a second region in the stack, the second region having one or both of a second temperature lower than a first temperature of the first region or a second refresh rate lower than a first refresh rate of the first region.

Method and apparatus for temperature-gradient aware data-placement for 3D stacked DRAMs

Systems, apparatuses, and methods for proactively managing inter-processor network links are disclosed. A computing system includes at least a control unit and a plurality of processing units. Each processing unit of the plurality of processing units includes a compute module and a configurable link interface. The control unit dynamically adjusts a clock frequency and a link width of the configurable link interface of each processing unit based on a data transfer size and layer computation time of a plurality of layers of a neural network so as to reduce execution time of each layer. By adjusting the clock frequency and the link width of the link interface on a per-layer basis, the overlapping of communication and computation phases is closely matched, allowing layers to complete more quickly.

Proactive management of inter-GPU network links

A plurality of thermal electric cooler (TEC) elements are formed in a TEC grid structure. Control logic dynamically varies a supply current supplied to each TEC element (or group of TEC elements) in the TEC grid based on changes in power density respectively associated with areas cooled by each of the TEC elements or group of TEC elements.

Runtime localized cooling of high-performance processors

An apparatus includes an integrated circuit chip with a set of circuits having two or more subsets of circuits; an external voltage regulator separate from the integrated circuit chip; two or more integrated voltage regulators on the integrated circuit chip that each provide an input voltage to a respective subset of the circuits; and a controller. The controller determines, using an integrated voltage regulator power loss model, an electrical power loss for the integrated voltage regulators for a first combination of operating points for the subsets of the circuits. The controller then determines, based on the electrical power loss, a second combination of operating points for the subsets of the circuits that includes an adjustment to an operating point for at least one of the subsets of the circuits that compensates for an electrical power loss of the corresponding integrated voltage regulator. The controller sets an operating point of each of the subsets of the circuits based on the second combination of operating points.

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Austin, TX, United States of America

Karthik Rao