Texas Instruments Corporation

Karthik Ramasubramanian

Karthik Subburaj

Sandeep Rao

Brian Paul Ginsburg

Sriram Murali

Jawaharlal Tangudu

Indu Prathapan

Pankaj Gupta

Jasbir Singh Nayyar

Shailesh Joshi

Raghu Ganesan

Sachin Bhardwaj

Deric Wayne Waters

Bijoy Bhukania

Krishnanshu Dandu

Sreekiran Samala

Daniel Colum Breen

Tom Altus

Tarkesh Pande

Arun Raghupathy

Sthanunathan Ramakrishnan

Arndt Mueller

Sunil Chomal

Anil Varghese Mani

Dheeraj Kumar Shetty

Sujaata Ramalingam

Shankar Narayanamoorthy

Hemanth Mullur

Kameswaran Vengattaramane

Anand Gadiyar

Jaiganesh Balakrishnan

Jayawardan Janardhanan

Sarma Sundareswara Gunturi

Goutam Dutta

Sachin Bharadwaj

Sachin Bharadwaj, Jr

Sandeep Kasargod

Jawaharial Tangudu

In some examples, a method includes receiving, at a first device, a radar signal transmitted by a second device at a transmission frequency offset from a local oscillator (LO) frequency of the first device by a target offset and reflected off a target. The method also includes determining an intermediate frequency (IF) of the radar signal based on the transmission frequency and the LO frequency. The method also includes determining a parts per million (ppm) offset between the first device and the second device based on the intermediate frequency and the target offset.

Estimating and compensating for crystal oscillator differences in a multi-crystal-oscillator radar

Systems and instruction carrying non-transitory processor-readable mediums are provided to facilitate access of radar data that may be scattered or non-uniformly located within a region of memory for further processing of such radar data. An example system includes counters that increment on different dimensions of the memory region, a lookup table, multipliers, an adder, and a wraparound mechanism to access different sets of non-contiguously stored radar data from a region of memory. The wraparound mechanism performs a wraparound operation when a combined address, generated by the adder based on addresses obtained by the multipliers, is greater than a last valid address in the region. The wraparound operation generates a new combined address that is used to fetch data from the memory. A transform operation is then performed on the fetched data.

Non-uniform multi-dimensional data access for radar data processing

A device includes a comparison circuit and a calculation circuit coupled to the comparison circuit. The comparison circuit is configured to receive a first digital input value (X) and a second digital input value (Y), and provide a first digital output value that indicates one of a first relationship, a second relationship, and a third relationship between X and Y. The calculation circuit is configured to receive X and Y, receive the first digital output value, and provide a second digital output value. The second digital output value is a first linear combination of X and Y responsive to the first digital output value indicating the first relationship, a second linear combination of X and Y responsive to the first digital output value indicating the second relationship, and a third linear combination of X and Y responsive to the first digital output value indicating the third relationship.

Linear approximation of a complex number magnitude

A radar system is provided that includes a compression component configured to compress blocks of range values to generate compressed blocks of range values, and a radar data memory configured to store compressed blocks of range values generated by the compression component.

Method and system for compression of radar signals

Methods, apparatus, systems and articles of manufacture to compensate radar system calibration are disclosed. A radio-frequency (RF) subsystem having a transmit channel, a receive channel, and a loopback path comprising at least a portion of the transmit channel and at least a portion of the receive channel, a loopback measurer to measure a first loopback response of the RF subsystem for a first calibration configuration of the RF subsystem, and to measure a second loopback response of the RF subsystem for a second calibration configuration of the RF subsystem, and a compensator to adjust at least one of a transmit programmable shifter or a digital front end based on a difference between the first loopback response and the second loopback response to compensate for a loopback response change when the RF subsystem is changed from the first calibration configuration to the second calibration configuration.

Methods and apparatus to compensate for radar system calibration changes

The disclosure provides a radar apparatus for estimating a range of an obstacle. The radar apparatus includes a local oscillator that generates a first ramp segment and a second ramp segment. The first ramp segment and the second ramp segment each includes a start frequency, a first frequency and a second frequency. The first frequency of the second ramp segment is equal to or greater than the second frequency of the first ramp segment when a slope of the first ramp segment and a slope of the second ramp segment are equal and positive. The first frequency of the second ramp segment is equal to or less than the second frequency of the first ramp segment when the slope of the first ramp segment and the slope of the second ramp segment are equal and negative.

Range resolution in FMCW radars

A system includes a hardware accelerator configured to perform a two-dimensional (2D) fast Fourier transform (FFT) on an M×N element array. The hardware accelerator has logM×N pipeline stages including an initial group of logM stages and a final group of logN stages. Each stage includes a butterfly unit, a FIFO buffer coupled to the butterfly unit, and a multiplier coupled to the butterfly unit and to an associated twiddle factor table. The hardware accelerator also includes butterfly control logic to provide elements of the M×N element array to the initial group of stages in an N direction of the array, and twiddle factor addressing logic to, for the twiddle factor tables of the initial group of stages, apply an indexed entry of the twiddle factor table to the associated multiplier. The indexed entry begins as a first entry and advances by N entries after every N cycles.

Two-dimensional FFT computation

A frequency modulated continuous wave (FMCW) radar system is provided that includes a receiver configured to generate a digital intermediate frequency (IF) signal, and an interference monitoring component coupled to the receiver to receive the digital IF signal, in which the interference monitoring component is configured to monitor at least one sub-band in the digital IF signal for interference, in which the at least one sub-band does not include a radar signal.

Interference detection in a frequency modulated continuous wave (FMCW) radar system

A Radix-3 butterfly circuit includes a first FIFO input configured to couple to a first FIFO. The circuit includes a first adder and first subtractor coupled to the first FIFO input, and a second FIFO input configured to couple to a second FIFO. The circuit includes a second adder and second subtractor coupled to the second FIFO input, and an input terminal coupled to the first adder and first subtractor. The circuit includes a first scaler coupled to the second adder and a first multiplexer, and a second scaler coupled to a third adder and second multiplexer. The circuit includes a third scaler coupled to a third subtractor and third multiplexer. An output of the first multiplexer is coupled to a complex multiplier. An output of the second multiplexer is coupled to a second FIFO output. An output of the third multiplexer is coupled to a first FIFO output.

Multi-dimensional FFT computation pipelined hardware architecture using Radix-3 and Radix-2butterflies

A system includes a memory configured to store a two-dimensional data structure that includes radar data arranged such that radar data of a first transmitter is separated from radar data of a second transmitter by a Doppler offset in the two-dimensional data structure. The system also includes a data fetch mechanism that includes a lookup table (LUT) applied on either of two dimensions. The lookup table is configured to store a data fetch location in the two-dimensional data structure, where the data fetch location indicates a location from which to fetch a subset of the radar data from the two-dimensional data structure and the data fetch mechanism is configured to fetch the subset of the radar data from the two-dimensional data structure based on the LUT. The system includes a processor configured to perform a fast Fourier transform (FFT) on the fetched subset of the radar data.

A system includes a shift register to store data samples, where the shift register includes a cell under test (CUT), a left guard cell, a right guard cell, a left window, and a right window. The system includes two sets of comparators to compare incoming data samples with data samples in the left window and the right window to compute ranks of the incoming data samples. The system includes a sorted index array to store a rank of the data samples in the shift register. The system includes a selector to select a Kth smallest index from the sorted index array and its corresponding data sample from the shift register. The system includes a target comparator, where the first comparator input receives a data sample from the CUT and the second comparator input receives a Kth smallest data sample, and the comparator output indicates a CFAR target detection.

CFAR OS detection hardware with two sets of comparators

A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.

Multiple chirp generation in a radar system

A radar system is provided that includes a receive channel configured to receive a reflected signal and to generate a first digital intermediate frequency (IF) signal based on the reflected signal, a reference receive channel configured to receive a reflected signal and to generate a second digital IF signal based on the reflected signal, and digital mismatch compensation circuitry coupled to receive the first digital IF signal and the second digital IF signal, the digital mismatch compensation circuitry configured to process the first digital IF signal and the second digital IF signal to compensate for mismatches between the receive channel and the reference receive channel.

Digital compensation for mismatches in a radar system

A FMCW radar system with a built-in self-test (BIST) system for monitoring includes a receiver, a transmitter, and a frequency synthesizer. A FMCW chirp timing engine controls timing of operations at least one radar component. The BIST system includes at least one switchable coupling for coupling a first plurality of different analog signals including from a first plurality of selected nodes in the receiver or transmitter that are all coupled to a second number of monitor analog-to-digital converters (ADCs). The second number is less than (&#x3c;) the first plurality of different analog signals. The BIST system includes a monitor timing engine and controller operating synchronously with the chirp timing engine, that includes a software configurable monitoring architecture for generating control signals including for selecting using the switchable coupling which analog signal to forward to the monitor ADC and when the monitor ADC samples the analog signals.

Field monitoring of analog signals in a radar system

Aspects of the present disclosure provide for a radar system including a radar IC including a timing engine, a local oscillator, and a modulator. The timing engine is configured to generate one or more chirp control signals. The local oscillator is configured to receive the one or more chirp control signals and generate a frame including a first sequence of chirps according to the one or more chirp control signals. The modulator is configured to modulate the first sequence of chirps to generate a second sequence of chirps so the frame includes the first sequence of chirps and the second sequence of chirps offset by a first frequency value.

Growing community of inventors

Bengaluru, India

Karthik Ramasubramanian