Freescale Semiconductor,inc.

Nxp Usa, Inc.

Karthik Ramanan

Jeffrey C Cunningham

Jon Scott Choy

Jacob Williams

Thomas D Cook

Padmaraj Sanjeevarao

Gilles Muller

Ronald J Syzdek

Cheong Min Hong

Ross Sinclair Scouller

Maurits Mario Nicolaas Storms

Gilles Joseph Maurice Muller

A memory includes read circuitry for reading values stored in memory cells. The read circuitry includes flipped voltage followers for providing bias voltages to nodes of current paths coupled to sense amplifiers during memory read operations.

Memory read circuitry with a flipped voltage follower

A memory includes a plurality of one-time programmable (OTP) memory cells, wherein each OTP memory cell includes a corresponding storage element capable of being in a permanently blown state or non-blown state. In the non-blown state, the corresponding storage element is capable of being in a low conductive state (LCS) or high conductive state (HCS). Control circuitry is configured to, in response to a received read request having a corresponding access address which selects a set of OTP memory cells, direct write circuitry to apply a voltage differential across the corresponding storage element of each selected OTP memory cell sufficient to set the corresponding storage element to a predetermined one of the LCS or HCS, and, after the write circuitry applies the voltage differential across the corresponding storage element, direct read circuitry to read the selected OTP memory cells to output read data stored in the selected OTP memory cells.

Memory with one-time programmable (OTP) cells and reading operations thereof

A non-volatile memory includes resistive cells, write circuitry, and write detect circuitry. Each resistive cell has a resistive storage element and is coupled to a corresponding first column line and corresponding second column line. The write circuitry is configured to provide a write current through a resistive storage element of a selected resistive memory cell during a write operation based on an input data value. The write detect circuitry is configured to generate a reference voltage using a voltage at the corresponding first column line coupled to the selected resistive memory cell at an initial time of the write operation, and, during the write operation, after the initial time, provide a write detect signal based on a comparison between the voltage at the corresponding first column line coupled to the selected resistive memory cell and the reference voltage, wherein the input data value is based on the write detect signal.

Non-volatile memory having write detect circuitry

A memory includes virtual ground circuitry configured to generate a virtual ground voltage (greater than zero volts) at a virtual ground node, a memory array of resistive memory cells in which each resistive memory cell includes a select transistor and a resistive storage element and is coupled to a first column line of a plurality of first column lines, and a first decoder configured to select a set of first column lines for a memory read operation from a selected set of the resistive memory cells. The memory includes read circuitry, and a first column line multiplexer configured to couple each selected first column line of the set of first column lines to the read circuitry during the memory read operation, and configured to couple each unselected first column line of the plurality of first column lines to the virtual ground node during the memory read operation.

Non-volatle memory with virtual ground voltage provided to unselected column lines during memory read operation

A non-volatile memory includes virtual ground circuitry configured to generate a virtual ground voltage at a virtual ground node, a memory array of memory cells in which each memory cell includes a select transistor and a storage element and is coupled to a first column line of a plurality of first column lines; and a first decoder configured to select a set of first column lines for a memory write operation to a selected set of the memory cells. The non-volatile memory also includes write circuitry configured to receive a write value for storage into the selected set of memory cells, and a first column line multiplexer configured to, during the memory write operation, couple each selected first column line of the set of first column lines to the write circuitry, and couple each unselected first column line of the plurality of first column lines to the virtual ground node.

Non-volatile memory with virtual ground voltage provided to unselected column lines during memory write operation

As disclosed herein, a memory includes an array of resistive memory cells and a voltage regulator circuit that provides a regulated voltage based on a circuit with a replica resistive storage element. The regulated voltage is applied to a mux transistor of a multiplexer of a column decoder that is used to select a particular column line of a memory array from a set of column lines to provide the proper voltage to the memory cell during a write operation to the memory cell.

Non-volatile memory with multiplexer transistor regulator circuit

A leakage measuring circuit includes a bias input node control circuit and provides a signal indicative of a leakage current through the bias input node. The bias input node control circuit includes a first input to receive an indication of a reference voltage, a second input to receive an indication of a voltage of the bias input node, and an output to bias the bias input node at the reference voltage based on a relationship between the first and second input. A well voltage bias circuit provides a well bias voltage and includes a well bias control circuit including a first input to receive the signal indicative of the leakage current, a second input to receive a signal indicative of a reference leakage current value, and an output for controlling the well bias voltage based on a relationship between the first and second input of the well bias control circuit.

Non-volatile memory with a well bias generation circuit

A sense amplifier circuit includes a reference path, a cell path, and a comparator circuit. The reference path includes a first current load device and a reference comparison node in which the reference path is coupled to a cell reference circuit during a read, wherein the first current load device includes a control input for controlling a current of the reference path. The cell path includes a second current load device and a cell comparison node in which the cell path is coupled to a memory cell during a read, wherein the second current load device includes a control input for controlling a current of the cell path. The comparator circuit indicates a data value being stored in the memory cell based on a comparison of voltages at the reference and cell comparison nodes. Different signals are provided to the control inputs of the first and second current load devices.

Reference generation for voltage sensing in a resistive memory

A word line regulator provides a write word line voltage for an asserted word line and includes a write replica circuit, a reference current path, and a regulator circuit. The write replica circuit is a replica of a write path for writing from a low to high resistance value of a resistive memory element of a memory cell. The word line regulator regulates the word line voltage at a value during the write operation of a low to high resistance value such that a select transistor of the memory cell is used as a source follower to regulate a first node of a resistive element of the memory cell being written. The first node is at a higher write voltage than a second node of the resistive element during the write operation, and the first node is located in a write path between the select transistor and the second node.

Non-volatile memory with a select gate regulator circuit

An output circuit, between a first power supply terminal and a second power supply terminal, receives a first logic signal that switches between a first logic state based on a voltage at the first power supply terminal and a second logic state based on a voltage at the second power supply terminal and provides a second logic signal, complementary to the first logic signal. A level translator is in a second power supply domain configured to have a second voltage differential between a third power supply terminal and a fourth power supply terminal, wherein the second voltage differential is greater than the first voltage differential. The level translator is designed so that it may be implemented using a subset of the transistors that have the shortest channel length and narrowest channel width.

Ratioless near-threshold level translator

A semiconductor memory device includes a non-volatile memory, a memory controller, and a charge pump system. The memory controller establishes first parameters for a first programming cycle of a first plurality of memory cells of the non-volatile memory prior to the first programming cycle being performed. The charge pump system includes a plurality of charge pumps and provides a first programming pulse for use in performing the first program cycle. The first programming pulse is provided by selecting, according to the first parameters, which of the plurality of charge pumps are to be enabled during the first program cycle and which are to be disabled during the first program cycle.

Smart charge pump configuration for non-volatile memories

An oscillator that includes a first source current leg and first sink current leg to source current and sink current, respectively, during a startup mode of oscillator operation. The oscillator includes a second source current leg and a second sink current leg to source current and sink current, respectively, during a second mode of oscillator operation.

Oscillator with startup circuitry

A method includes forming a first conductive layer over a substrate in a first region and second region of the substrate; patterning the first conductive layer to form a select gate in the first region and to remove the first conductive layer from the second region; forming a charge storage layer over the select gate and the substrate in the first region and over the substrate in the second region; forming a second conductive layer over the charge storage layer in the first and second regions; and patterning the second conductive layer and charge storage layer to form a control gate overlapping the select gate in the first region, wherein a first portion of the charge storage layer remains between the select gate and control gate, and to form an electrode in the second region, wherein a second portion of the charge storage layer remains between the electrode and substrate.

Split-gate non-volatile memory (NVM) cell and device structure integration

A compensated hysteresis circuit comprises a hysteresis circuit including an output node and a first control transistor. The first control transistor provides feedback to the hysteresis circuit. A temperature and voltage compensation circuit includes a self-biasing threshold control circuit including an input coupled to the output node of the hysteresis circuit, and a first trim transistor coupled between the first control transistor of the hysteresis circuit and the self-biasing threshold control circuit.

Compensated hysteresis circuit

A negative charge pump is responsive to a pump enable signal. A voltage controlled current source provides a current. A resistor is coupled between a node from the voltage controlled current source and a negative charge output from the negative charge pump. A capacitor is placed in parallel with the resistor. A comparator generates the pump enable signal to control the negative charge pump. The comparator is coupled to the resistor and the capacitor and measures an IR drop thereacross and compares this measurement against a reference threshold. A level of the pump enable signal can be variable by tuning an amount of resistance of the resistor or capacitor or adjusting the reference threshold. A memory can be driven by a method of the negative charge pump.

Growing community of inventors

Austin, TX, United States of America

Karthik Ramanan