Apple Inc.

Karthik Rajagopal

Shingo Suzuki

Bo Tang

John H Mylius

Antonietta Oliva

Suparn Vats

Muthukumaravelu Velayoudame

Manoj Gopalan

Sambasivan Narayan

Amit Chandra

Mini Nanua

Narayanan V Thondugulam

Praveen Bhutani

Rahul Sharma

Sunil Mehta

A method for designing a clock tree is disclosed. In one embodiment, a preliminary clock tree design for an integrated circuit (IC) is processed. The clock tree includes a root node, a number of intermediate levels, and a leaf level that is coupled to a number of clocked circuits. Clock gating circuits are placed at the leaf level of the clock tree, and at least some of the intermediate levels. Processing the preliminary clock tree design includes ensuring that an equal number of clock gating circuits are coupled between each leaf level clock gating circuit and the root node. After processing the preliminary clock tree design, clock tree synthesis is performed by executing a clock tree synthesis tool on a computer system to generate a synthesized clock tree design.

Level balanced clock tree

A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

Area efficient power switch

Embodiments of an electromigration (EM) check scheme to reduce a pessimism on current density limits by checking wire context. This methodology, in an embodiment, includes applying existing electronic design automation (EDA) flows and tools to identify potentially-failing wires based on a worst-case EM check using conservative foundry current density limits. A more accurate, context-specific check can be performed on the potentially-failing wires to eliminate one or more of the potentially-failing wires if those wires do not experience worst-case conditions and meet current density limits based on an actual context of those wires. A designer can correct remaining wires which are not eliminated by the context-specific check.

Context-aware reliability checks

In an embodiment, a methodology for designing an integrated circuit that attempts to improve power efficiency is provided. The methodology includes simulating the design under one or more power stimuli, where the power stimuli are known to cause high power consumption (e.g. in previous designs of the integrated circuit, the power stimuli may have caused power consumption). A set of nets within the integrated circuit may be identified that have the highest activity in the simulation (e.g. the highest amount of switching). The methodology may include providing data to the routing tool that is to route the nets in the integrated circuit. The data may indicate constraints for the set of nets, to help reduce dynamic power on these nets. Power efficiency of the integrated circuit may be improved if the routing tool is able to honor the constraints.

Activity-driven capacitance reduction to reduce dynamic power consumption in an integrated circuit

Techniques are disclosed for partitioning a placement of a circuit design into a plurality of regions. A constraint is generated based on the partitioning of the placement and on the sequential elements that are located within each region. The constraint is provided to one or more design tools, and the constraint forces sequential elements to fall within the same region on the next placement. Some regions can be classified as guides, and these regions act as a recommendation for a design tool instead of as an explicit rule. Other regions can be classified as inclusive, and sequential elements can be allowed to enter the region but any sequential elements already in the region must stay in the region. Further regions can be classified as exclusive, and no sequential elements may enter or leave these regions on the next placement of the circuit design.

Micro-regions for auto place and route optimization

Growing community of inventors

Mountain View, CA, United States of America

Karthik Rajagopal