Advanced Micro Devices Corporation

Nvidia Corporation

Karthik Natarajan

Spencer Montgomery Gold

Jun Yang

Lei Wang

Stephen Victor Kosonocky

Stephen Felix

Ge Yang

Hua Chen

Hwong-Kwo Lin

Jing Guo

Eric H Voelkel

Joel Thornton Irby

Andreas J Gotterba

Eric W Busta

Haiyan Gong

Jason Golbus

Gregory A Constant

Zhenye Jiang

Michael C Braganza

Brian M Lay

Ravi T Jotwani

Beibei Ren

Giridhar Narayanaswami

A register file includes a substrate, a plurality of entries, and a plurality of read ports. Each entry includes a corresponding subset of a plurality of memory cells defined on the substrate. Each read port includes a plurality of access elements defined on the substrate. Each access element is associated with a particular common bit position of each of the entries. A plurality of entry access groups are disposed in adjacent columns on the substrate. Each entry access group is associated with a corresponding one of the plurality of entries and includes the access elements for all of the read ports for the corresponding entry.

Register file with read ports clustered by entry

A subsystem is configured to apply a voltage source to a gated circuit domain in a manner that limits in-rush current and affords minimal time delay. A control signal turns on a wake-up switch that connects the voltage source to the domain. The equivalent series resistance of the wake-up switch has a magnitude that limits the transient charge current to the gated domain. A digital control circuit monitors the resulting rising domain voltage and determines when the domain voltage reaches operating level, at which point additional transient current will be minimal. The control circuit then activates a primary switch that connects the voltage source to the domain through a series resistance of negligible magnitude. An adjustment element provides the option to permanently set a control signal that marginally reduces the time at which the control circuit activates the primary switch to compensate for variations in circuit parameters.

In-rush current limiting switch control

A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.

Power savings via selection of SRAM power source

A content addressable memory (CAM) of a data processing device can operate in a normal mode or a test mode. In the normal mode, the CAM provides a match value in response to determining that a received data value matches one of a plurality of values stored at memory locations of the CAM. In a test mode of operation, a plurality of test signals are applied to the CAM, and the CAM provides a match value in response to assertion of one of the test signals. The match value is applied to a functional module associated with the CAM to determine a test result. Accordingly, the test signals applied to the CAM provide a flexible way to generate match values and apply those values to the functional module during testing of the data processing device.

Content addressable memory match signal test device and methods thereof

A circuit including is disclosed. The circuit includes a precharge circuit configured to pull a dynamic node toward a voltage present on the voltage supply node during a precharge phase, and an evaluation circuit configured to, during an evaluation phase, pull the dynamic node toward a ground voltage responsive to a first input condition and configured to inhibit pulling of the dynamic node down responsive to a second input condition. A pull-up circuit coupled between the first dynamic node and the voltage supply node includes first and second pull-up transistors. The first pull-up transistor is configured to activate responsive to the precharge phase. The second pull-up transistor is configured to activate at a delay time subsequent to entry of the evaluation phase. When the first and second pull-up transistors are active, a pull-up path is provided between the dynamic node and the voltage supply node.

Dynamic logic circuit with device to prevent contention between pull-up and pull-down device

Growing community of inventors

Austin, TX, United States of America

Karthik Natarajan