Delphi Technologies IP Limited

Karthik Naik

Venkata Jaya Sai Praneeth Ammanamanchi

Miang Keng Yoon

Wong Chuan Ming

Neil Van Zyl

Engel Joseph

A discrete relay driver circuit that includes a first high side gate drive circuit configured to drive a first high side MOSFET and a second high side gate drive circuit configured to drive a second high side MOSFET. The discrete relay driver circuit also includes a first resistor divider configured to sense voltage from the first high side MOSFET, a second resistor divider configured to sense voltage from the second high side MOSFET, and a first low side gate driver circuit configured to drive a first low side MOSFET. The discrete relay driver circuit also includes a second low side gate driver circuit configured to drive a second low side MOSFET based on a first low side enable signal, and a third low side gate driver circuit configured to drive a third low side MOSFET based on a second low side enable signal.

Discrete relay driver circuit for peak and hold operation

A system includes a control board comprising: a microprocessor configured to output a PWM signal; a primary shutoff path circuit, an upper MOSFET shutoff circuit, and a lower MOSFET shutoff circuit, each of the circuits configured to receive the PWM signal; a first buffer provided at an output of the primary shutoff path circuit; a second buffer provided at an output of the upper MOSFET shutoff circuit; a third buffer provided at an output of the lower MOSFET shutoff circuit; a first resistor and a second resistor provided in parallel at the first buffer and configured to provide a first feedback signal; a third resistor and a fourth resistor provided in parallel at the second buffer and configured to provide a second feedback signal; and a fifth resistor and a sixth resistor provided in parallel at the third buffer and configured to provide a third feedback signal.

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Singapore, Singapore

Karthik Naik