Qualcomm Incorporated

Samsung Electronics Co., Ltd.

Maxim Integrated Products, Inc.

Karthik Nagarajan

Chao Song

Zhengzheng Wu

Kee-Bong Song

Pranav Dayal

Hou-Shin Chen

Mustafa Ertugrul Oner

Debesh Bhatta

Sung-En Chiu

Ying Hai Chen

Ning Bi

Yang Zhou

Dinesh Jagannath Alladi

Jeffrey Mark Hinrichs

Andrew Weil

Kevin Jia-Nong Wang

Yi-Hung Tseng

Chenling Huang

John Abcarius

Christian Venerus

A method of controlling power in a transmission system may include determining a first transmit power of a first transmit path, determining a second transmit power of a second transmit path, and controlling the first transmit path and the second transmit path based on a combination of the first transmit power and the second transmit power. The combination of the first transmit power and the second transmit power may include a sum of the first transmit power and the second transmit power. Controlling the first transmit path and the second transmit path may include determining a first effective power target for the first transmit path based on the first transmit power and the second transmit power, and determining a second effective power target for the second transmit path based on the first transmit power and the second transmit power.

Systems, methods, and apparatus for combined power control of multiple transmit paths

A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.

Power and area efficient digital-to-time converter with improved stability

A digital phase-frequency detector characterizes a delay between two input clock signals using a ring oscillator. A cycle count of a ring oscillator signal circulating through a loop in the ring oscillator during the delay provides a coarse measurement of the delay. A phase of the ring oscillator signal in the loop at the end of the delay provides a fine measurement of the delay. A digital phase-locked loop may control an oscillation frequency of a digitally-controlled oscillator responsive to the fine measurement of the delay and control a division within a clock divider responsive to the coarse measurement of the delay.

Digital phase-frequency detector with split control loops for low jitter and fast locking

Techniques and systems are provided for tracking objects in one or more video frames. For example, a first set of one or more bounding regions are determined for a video frame based on a trained classification network applied to the video frame. The first set of one or more bounding regions are associated with one or more objects in the video frame. One or more blobs can be detected for the video frame. A blob includes pixels of at least a portion of an object in the video frame. A second set of one or more bounding regions are determined for the video frame that are associated with the one or more blobs. A final set of one or more bounding regions is determined for the video frame using the first set of one or more bounding regions and the second set of one or more bounding regions. Object tracking can then be performed for the video frame using the final set of one or more bounding regions.

Methods and systems for applying complex object detection in a video analytics system

A digital to analog converter (DAC) includes a plurality of DAC transistor devices having an input side configured to be selectively coupled to a system voltage based on a digital input signal and an output side configured to provide an analog output signal, a plurality of non-DAC transistor devices coupled to the input side of the DAC transistor devices, the non-DAC transistor devices configured as variable resistances, and a control circuit configured to adjust a bias of the non-DAC transistor devices.

Digital-to-analog converter

Certain aspects of the present disclosure provide apparatus and techniques for digital-to-analog conversion. One example apparatus generally includes a first digital-to-analog converter (DAC) having an input coupled to a digital input node of the apparatus, a second DAC, a digital processor coupled between the digital input node and an input of the second DAC, and a combiner coupled to the first DAC and the second DAC.

Partitioned digital-to-analog converter system

A method and apparatus for reducing the amount of jitter in a signal are disclosed. In one embodiment a feed-forward loop compares the edges of a reference clock and an input signal, converts a time difference of the compared edges into a voltage signal, and controls a time delay in a voltage controlled delay line in order to reduce or eliminate jitter.

Phase-locked loop output adjustment

A method and apparatus for controlling supply voltage for a successive approximation register analog to digital converter and comparator common mode voltage. The method comprises: measuring a successive approximation register conversion time; comparing the successive approximation register conversion time with a desired conversion time; and if necessary, performing a closed loop adjustment of at least one of the supply and/or comparator common mode voltage. The apparatus consists of a common mode voltage and regulator correction module. The common mode voltage and regulator correction module includes a phase frequency detector, a charge pump and may include a transconductance cell.

Method and apparatus for closed loop control of supply and/or comparator common mode voltage in a successive approximation register analog to digital converter

An apparatus for generating a pulse having a pulse width substantially independent of process variation in resistive and capacitive values. The apparatus includes a PTAT current source to generate a first current to charge a capacitor to produce a first voltage; a &#x394;VGS current source to generate a second current through a resistor to produce a second voltage V; a comparator to generate the pulse in response to the first and second voltages; and a circuit to enable the charging and discharging of the capacitor. The use of the distinct current sources (e.g., PTAT and &#x394;VGS) enables the pulse generator to be configured substantially process independent of resistive value. The use of a MOSFET capacitor for the capacitor enables the pulse generator to be made substantially process independent of capacitive value. An additional bandgap current source in parallel with the &#x394;VGS current source reduces the pulse width dependency on temperature.

Growing community of inventors

Santa Clara, CA, United States of America

Karthik Nagarajan