Intel Corporation

Karthik Kumar

Francesc Guim Bernat

Thomas Willhalm

Mark A Schmisseur

Timothy Verrall

Ned M Smith

Raj K Ramanujan

Suraj Prabhakaran

Marcos Emanuel Carranza

Susanne M Balle

Kshitij Arun Doshi

Rajesh Poornachandran

Brinda Ganesh

Brian J Slechta

Andrew J Herdrich

Daniel Rivas Barragan

Patrick G Kutch

Mustafa Hajeer

Rahul Khanna

Narayan Ranganathan

Patrick Lu

Rashmin N Patel

Monica Kenguva

Benjamin Graniello

Alexander Vul

Martin P Dimitrov

Alexander Bachmutsky

Cesar Martinez-Spessot

Ignacio Astilleros Diez

Felipe Pastor Beneyto

Vincent J Zimmer

Mohan J Kumar

Robert G Blankenship

Sujoy Sen

Ramanathan Sethuraman

Subrata Banik

Petar Torre

Evan Custodio

Edwin Verplanke

Mateo Guzman

Anil Rao

Nicolas A Salhuana

Ginger Gilsdorf

Kapil Sood

John Joseph Browne

Tarun Viswanathan

Dimitrios Ziakas

Trevor Cooper

John Chun Kwok Leung

Rita D Gupta

Nicolae Octavian Popovici

Patrick Bohan

Ravi L Sahita

Rita H Wouhaybi

Murugasamy K Nachimuthu

Pete D Vogt

Philip R Lantz

Lidia Warnes

Chandan Egbert

Slawomir Putyrski

Nilesh K Jain

Durgesh Srivastava

Shrikant M Shah

Amin Firoozshahian

Zhongyan Lu

Donald L Faw

Ravi Iyer

Uzair Qureshi

Tushar Gohad

Lakshmi N Talluru

Francois Dugast

Ben McCahill

Mark D Tetreault

Steven Briscoe

Kevin Bohan

Kirill Instrumentov

Implementation of object versioning and consistency at scale is described. An example of a computer-readable storage medium includes instructions to receive a storage request from an object management authority to store a version of a data object at a storage appliance; generate a hash value of the data object; store the data object in a scratchpad storage; transmit a verification request for the hash value of the data object to an object versioning authority; and, upon receiving affirmative verification for the hash value, move the data object from the scratchpad storage to a media storage and transmit an acknowledgement to the object management authority.

Implementation of object versioning and consistency at scale

Systems, apparatuses, and methods provide for memory management where an infrastructure processing unit bypasses a central processing unit. Such an infrastructure processing unit determines if incoming packets of memory traffic trigger memory rules stored by the infrastructure processing unit. The incoming packets are routed to the central processing unit in a default mode when the incoming packets do not trigger the memory rules. Conversely, the incoming packets are routed to the infrastructure processing unit and bypass the central processing unit in an inline mode when the incoming packets trigger the memory rules. A memory architecture communicatively coupled to the central processing unit receives a set of atomic transactions from the infrastructure processing unit that bypasses the central processing unit and performs the set of atomic transactions from the infrastructure processing unit.

Memory schemes for infrastructure processing unit architectures

An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller to allocate a first secure portion of a pooled memory to a first instantiation of an application on a first node, and circuitry coupled to the one or more substrates and the controller, the circuitry to provide a failover interface for a second instantiation of the application on a second node to access the first secure portion of the pooled memory in the event of a failure of the first node. Other embodiments are disclosed and claimed.

Failover for pooled memory

A system comprising a traffic handler comprising circuitry to determine that data of a memory request is stored remotely in a memory pool; generate a packet based on the memory request; and direct the packet to a path providing a guaranteed latency for completion of the memory request.

Memory pooled time sensitive networking based architectures

Methods, apparatus, systems and articles of manufacture are disclosed for edge data prioritization. An example apparatus includes at least one memory, instructions, and processor circuitry to at least one of execute or instantiate the instructions to identify an association of a data packet with a data stream based on one or more data stream parameters included in the data packet corresponding to the data stream, the data packet associated with a first priority, execute a model based on the one or more data stream parameters to generate a model output, determine a second priority of at least one of the data packet or the data stream based on the model output, the model output indicative of an adjustment of the first priority to the second priority, and cause transmission of at least one of the data packet or the data stream based on the second priority.

Systems, apparatus, and methods for edge data prioritization

Methods and apparatus for application aware memory patrol scrubbing techniques. The method may be performed on a computing system including one or more memory devices and running multiple applications with associated processes. The computer system may be implemented in a multi-tenant environment, where virtual instances of physical resources provided by the system are allocated to separate tenants, such as through virtualization schemes employing virtual machines or containers. Quality of Service (QoS) scrubbing logic and novel interfaces are provided to enable memory scrubbing QoS policies to be applied at the tenant, application, and/or process level. This QoS policies may include memory ranges for which specific policies are applied, as well as bandwidth allocations for performing scrubbing operations. A pattern generator is also provided for generating scrubbing patterns based on observed or predicted memory access patterns and/or predefined patterns.

Application aware memory patrol scrubbing techniques

The platform data aging for adaptive memory scaling described herein provides technical solutions for technical problems facing power management for electronic device processors. Technical solutions described herein include improved processor power management based on a memory region life-cycle (e.g., short-lived, long-lived, static). In an example, a short-term memory request is allocated to a short-term memory region, and that short-term memory region is powered down upon expiration of the lifetime of all short-term memory requests on the short-term memory region. Multiple memory regions may be scaled down (e.g., shut down) or scaled up based on demands for memory capacity and bandwidth.

Platform data aging for adaptive memory scaling

Examples described herein relate to a switch device. The switch device can perform replication of content stored in a source memory region to two or more memory regions available from two or more nodes, wherein the two or more memory regions available from two or more nodes are identified to the circuitry for use to store replicated content. The two or more nodes can be on different racks than that of a memory device that stores the source memory region. The switch device can select the two or more memory regions available from two or more nodes based, at least, in part on resiliency criteria associated with the two or more nodes.

High-availability memory replication in one or more network devices

A multi-tenant dynamic secure data region in which encryption keys can be shared by services running in nodes reduces the need for decrypting data as encrypted data is transferred between nodes in the data center. Instead of using a key per process/service, that is created by a memory controller when the service is instantiated (for example, MKTME), a software stack can specify that a set of processes or compute entities (for example, bit-streams) share a private key that is created and provided by the data center.

Multi-tenant isolated data regions for collaborative platform architectures

In one embodiment, an apparatus includes an interface to couple a plurality of devices of a system, the interface to enable communication according to a Compute Express Link (CXL) protocol, and a power management circuit coupled to the interface. The power management circuit may: receive, from a first device of the plurality of devices, a request according to the CXL protocol for updated power credits; identify at least one other device of the plurality of devices to provide at least some of the updated power credits; and communicate with the first device and the at least one other device to enable the first device to increase power consumption according to the at least some of the updated power credits. Other embodiments are described and claimed.

System, apparatus and methods for power communications according to a CXL power protocol

System and techniques for power-based adaptive hardware reliability on a device are described herein. A hardware platform is divided into multiple partitions. Here, each partition includes a hardware component with an adjustable reliability feature. The several partitions are placed into one of multiple reliability categories. A workload with a reliability requirement is obtained and executed on a partition in a reliability category that satisfies the reliability requirements. A change in operating parameters for the device is detected and the adjustable reliability feature for the partition is modified based on the change in the operating parameters of the device.

Power-based adaptive hardware reliability on a device

Embodiments described herein are generally directed to the use of sidecars to perform dynamic Application Programming Interface (API) contract generation and conversion. In an example, a first sidecar of a source microservice intercepts a first call to a first API exposed by a destination microservice. The first call makes use of a first API technology specified by a first contract and is originated by the source microservice. An API technology is selected from multiple API technologies. The selected API technology is determined to be different than the first API technology. Based on the first contract, a second contract is dynamically generated that specifies an intermediate API that makes use of the selected API technology. A second sidecar of the destination microservice is caused to generate the intermediate API and connect the intermediate API to the first API.

Dynamic application programming interface (API) contract generation and conversion through microservice sidecars

Methods and apparatus for software-defined coherent caching of pooled memory. The pooled memory is implemented in an environment having a disaggregated architecture where compute resources such as compute platforms are connected to disaggregated memory via a network or fabric. Software-defined caching policies are implemented in hardware in a processor SoC or discrete device such as a Network Interface Controller (NIC) by programming logic in an FPGA or accelerator on the SoC or discrete device. The programmed logic is configured to implement software-defined caching policies in hardware for effecting disaggregated memory (DM) caching in an associated DM cache of at least a portion of an address space allocated for the software application in the disaggregated memory. In connection with DM cache operations, such as cache lines evicted from a CPU, logic implemented in hardware determines whether a cache line in a DM cache is to be evicted and implements the software-defined caching policy for the DM cache including associated memory coherency operations.

Software-defined coherent caching of pooled memory

Techniques for expanded trusted domains are disclosed. In the illustrative embodiment, a trusted domain can be established that includes hardware components from a processor as well as an off-load device. The off-load device may provide compute resources for the trusted domain. The trusted domain can be expanded and contracted on-demand, allowing for a flexible approach to creating and using trusted domains.

Technologies for expanded trusted domains

Methods and apparatus for scale out hardware-assisted tracing schemes for distributed and scale-out applications. In connection with execution of one or more applications using a distributed processing environment including multiple compute nodes, telemetry and tracing data are obtained using hardware-based logic on the compute nodes. Processes associated with applications are identified, as well as the compute nodes on which instances of the processes are executed. Process instances are associated with process application space identifiers (PASIDs), while processes used for an application are associating with a global group identifier (GGID) that serves as an application ID. The PASIDs and GGIDs are used to store telemetry and/or tracing data on the compute nodes and/or forward such data to a tracing server in a manner that enables telemetry and/or tracing data to be aggregated on an application basis. Telemetry and/or tracing data may be obtained from processors on the compute nodes, and (optionally) additional elements such as network interface controllers (NICs). Tracing data may also be obtained from switches used for forwarding data between processes.

Hardware-assisted tracing schemes for distributed and scale-out applications

Growing community of inventors

Chandler, AZ, United States of America

Karthik Kumar