Globalfoundries Inc.

Karthik Chandrasekaran

Jagar Singh

Kevin J Yang

Zhi-Yuan Wu

Biswanath Senapati

Sriram Balasubramanian

Lingquan Wang

Juhi Bansal

Vineet Wason

Varsha Balakrishnan

Arunima Dasgupta

Structures and methods to minimize parasitic capacitance in a circuit structure are provided. The structure may include a substrate supporting one or more circuits and one or more metallization layers above the substrate. The metallization layer includes a conductive pattern defined by an array of conductive fill elements, where the conductive fill elements of the array are discrete, electrically isolated elements sized to satisfy, at least in part, a pre-defined minimum area-occupation ratio for a chemical-mechanical polishing of the metallization layer, and to minimize parasitic capacitance within the metallization layer, as well as minimize parasitic capacitance between the metallization layer and the circuit, and if multiple metallization layers are present, between the layers.

Metallization layers configured for reduced parasitic capacitance

Worst case performance of an SRAM cell may be simulated more accurately with less intensive computations. An embodiment includes determining, by a processor, a process corner G of an SRAM cell, having pull-down, pass-gate, and pull-up devices, process corner G being defined as the worst performance of the cell when only global variations of parameters of the SRAM cell are included, setting each of the pull-down, pass-gate, and pull-up devices at process corner G, performing, on the processor, a number of Monte Carlo simulations of the SRAM cell devices around process corner G with only local variations of the parameters, generating a normal probability distribution for Ibased on the local Monte Carlo simulations around process corner G, extrapolating the worst case Ifrom the normal probability distribution of Ito define a process corner SRM representing a slowest SRAM bit on a chip, and validating an SRAM cell based on the SRM corner. Embodiments further include creating a library of SRM corner values for multiple SRAM cells, and validating an SRAM cell by selecting an SRM corner from the library. Embodiments further include linearly scaling the SRM corner value with global sigma input variations from 0 sigma to 6 sigma and/or with local sigma input variations from 0 sigma to 6 sigma, selecting a scaled SRM corner value at the sigma corresponding to design and memory size requirements for the SRAM cell, simulating the scaled SRM corner by a processor, and employing the simulated scaled SRM corner to validate performance of an SRAM cell.

Model library implementation and methodology for worst case performance modeling for SRAM cells

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Albany, NY, United States of America

Karthik Chandrasekaran