International Business Machines Corporation

Adeia Semiconductor Bonding Technologies Inc.

Elpis Technologies Inc.

Karthik Balakrishnan

Alexander Reznicek

Pouya Hashemi

Kangguo Cheng

Bahman Hekmatshoartabari

Tak H Ning

Jeng-Bang Yau

Stephen W Bedell

Jeffrey W Sleight

Michael A Guillorn

Keith E Fogel

Isaac Lauer

Tenko Yamashita

Takashi Ando

Keith Aelwyn Jenkins

Sanghoon Lee

Ali Afzali-Ardakani

Josephine B Chang

Sivananda K Kanakasabapathy

Ali Khakifirooz

Nicolas J Loubet

John Albrecht Ott

Barry P Linder

Lukas Czornomaz

Paul S Chang

David James Frank

John Bruley

Christos Vezyrtzis

Clint Oteri

Ruilong Xie

Bruce Bennett Doris

Kevin K Chan

Bruce Martin Fleischer

Mahmoud M Khojasteh

Martin O Sandberg

Abram L Falk

Methods and systems for mitigating the effects of defects in a quantum processor are provided. A mitigation system includes a quantum processor comprising a plurality of qubits. The system includes a light emitting source that can be tuned to produce light pulses of different wavelengths. The system includes an array of bandpass filters. Each bandpass filter is aligned with a qubit on the quantum processor and has a unique pass band. The system may include a controller configured to receive a selection of a qubit and to tune the light emitting source to emit a light pulse having a wavelength that falls within a range of a bandpass filter that is aligned with the selected qubit. The light pulse is used to scramble an ensemble of strongly coupled two-level system (TLS) in the processor.

Selective optical tuning of qubit two-level system interactions using bandpass filters

Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a superconducting circuit provided on an encapsulated vacuum cavity are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise a superconducting circuit provided on the encapsulated vacuum cavity.

Superconducting circuit provided on an encapsulated vacuum cavity

A method of forming two or more nano-sheet devices with varying electrical gate lengths, including, forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate, removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess having a recess depth in the at least one alternating nano-sheet channel layers, where the recess depth is greater than the indentation depth.

Fabrication of nano-sheet transistors with different threshold voltages

A Junction Field Effect Transistor (JFET) has a source and a drain disposed on a substrate. The source and drain have an S/D doping with an S/D doping type. Two or more channels are electrically connected in parallel between the source and drain and can carry a current between the source and drain. Each of the channels has two or more channel surfaces. The channel has the same channel doping type as the S/D doping type. A first gate is in direct contact with one of the channel surfaces. One or more second gates is in direct contact with a respective second channel surface. The gates are doped with a gate doping that has a gate doping type opposite of the channel doping type. A p-n junction (junction gate) is formed where the gates and channel surfaces are in direct contact. The first and second gates are electrically connected so a voltage applied to the first and second gates creates at least two depletion regions in each of the channels. In some embodiments, the junction gates are formed all-around the channel surfaces. As a result, the current flowing in the channels between the source and drain can be controlled with less voltage applied to the gates and less power consumption.

Low voltage/power junction FET with all-around junction gate

A structure including a three-dimensionally stretchable single crystalline semiconductor membrane located on a substrate is provided. The structure is formed by providing a three-dimensional (3D) wavy silicon germanium alloy layer on a silicon handler substrate. A single crystalline semiconductor material membrane is then formed on a physically exposed surface of the 3D wavy silicon germanium alloy layer. A substrate is then formed on a physically exposed surface of the single crystalline semiconductor material membrane. The 3D wavy silicon germanium alloy layer and the silicon handler substrate are thereafter removed providing the structure.

Three-dimensionally stretchable single crystalline semiconductor membrane

A semiconductor structure may include two vertical transport field effect transistors comprising a top source drain, a bottom source drain, and an epitaxial channel and a resistive random access memory between the two vertical transport field effect transistors, the resistive random access memory may include an oxide layer, a top electrode, and a bottom electrode, wherein the oxide layer may contact the top source drain of the two vertical field effect transistor. The top source drain may function as the bottom electrode of the resistive random access memory. The semiconductor structure may include a shallow trench isolation between the two vertical transport field effect transistors, the shallow trench isolation may be embedded in a first spacer, a doped source, and a portion of a substrate.

Resistive random access memory integrated with vertical transport field effect transistors

Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a vacuum encapsulated Josephson junction are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise one or more superconducting components of a superconducting circuit provided inside the encapsulated vacuum cavity.

Vacuum encapsulated Josephson junction

A Vertical Field Effect Transistor (VFET) and/or a one transistor dynamic random access memory 1T DRAM that has a substrate with a horizontal substrate surface, a source disposed on the horizontal substrate surface, a drain, and a channel. The channel has a channel top, a channel bottom, a first channel side, a second channel side, and two channel ends. The channel top is connected to the drain. The channel bottom is connected to the source. The channel is vertical and perpendicular to the substrate surface. A first gate stack interfaces with the first channel side and a second gate stack interfaces with the second channel side. A single external gate connection electrically connects the first gate stack and the second gate stack A gate bias (voltage) applied on the single external gate connection biases the first channel side in accumulation and biases the second channel side in inversion. The first gate stack is made of a first high-k dielectric layer and a first gate metal layer. The second gate stack is made of a second high-k dielectric layer and a second gate metal layer. The single external gate electrical connection is made to the first gate metal layer and the second gate metal layer. The first and second channel side can be made of the same or different materials. The first and second gate metal layer can be made of the same or different materials. One of the channel ends forms a floating body region, i.e. a capacitance, used by the 1T DRAM.

Vertical transistor floating body one transistor DRAM memory cell

A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.

Stacked vertical transport field effect transistor electrically erasable programmable read only memory (EEPROM) devices

A method of manufacturing a vertical transistor device comprises forming a bottom source region on a semiconductor substrate, forming a channel region extending vertically from the bottom source region, forming a top drain region on an upper portion of the channel region, forming a first gate region having a first gate length around the channel region, and forming a second gate region over the first gate region and around the channel region, wherein the second gate region has a second gate length different from the first gate length, and wherein at least one dielectric layer is positioned between the first and second gate regions.

Twin gate tunnel field-effect transistor (FET)

A tilted nanowire structure is provided which has an increased gate length as compared with a horizontally oriented semiconductor nanowire at the same pitch. Such a structure avoids complexity required for vertical transistors and can be fabricated on a bulk semiconductor substrate without significantly changing/modifying standard transistor fabrication processing.

Tilted nanowire transistor

A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, a silicide layer is formed on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor. The silicide layer electrically connects the first and second drain regions to each other.

Stacked vertical transistor erasable programmable read-only memory and programmable inverter devices

A first vertical T-FET has a source heavily doped with a source concentration of a source-type dopant, a drain doped with a drain concentration of a drain-type dopant, and a channel between the source and drain. The source, channel, and drain are stacked vertically in a fin or pillar perpendicular to a substrate. A gate stack encompasses the channel sides and has a drain overlap amount overlapping the drain sides and a source overlap amount overlapping the source sides. External contacts electrically connect the gate and source and/or drain. The source-type dopant and the drain-type dopant are opposite dopant types. In some embodiments, a second vertical T-FET is stacked on the first vertical T-FET. Different VT-FET devices are made by changing the materials, doping types and levels, and connections to the sources, channels, and drains. Device characteristics are designed/changed by changing the amount of source and drain overlaps of the gate stack(s).

Stacked vertical tunnel FET methods

An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.

Diode connected vertical transistor

A cross-coupled inverter made of nanolayers from a nanosheet stack structure has a left field effect transistor (FET) stack and a right FET stack. The left FET stack has a second left FET stacked on a first left FET. The first and second left FETs have opposite types. The right FET stack has a second right FET stacked on a first right FET. The first and second right FETs have opposite types. The first left and first right FET have a first common source drain (S/D). The left FET stack has a left gate stack surrounding the one or more first left FET channel layers and the one or more second left FET channel layers. The right FET stack has a right gate stack surrounding the one or more first right FET channel layers and the one or more second right FET channel layers. In some embodiments the left/right gate stack has a left/right center gate stack layer and one or more left/right gate stack layers. The center gate stack layers are thicker than the gate stack layers and are between the first and second FETs. The insulating layer surrounds the middle of the center gate stack layers. The first right FET S/D and the second right FET S/D are internally and electrically connected and connected to a Q external connection. The Q external connection is externally connected to the left gate stack. The first left FET S/D and the second left FET S/D are internally, electrically connected together and connected to a QB external connection. The QB external connection is externally connected to the right gate stack. During operation, the first common S/D is connected to a first external power contact and the second common S/D is connected to a second external power contact and the Q external connection has a logically opposite value of the QB external connection during a desired operation phase. Chip area is reduced because of the low number of external connections required to wire the cross-coupled inverter device.

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White Plains, NY, United States of America

Karthik Balakrishnan