Other

Vayavya Labs Private Limited

Karthick Gururaj

Sandeep Pendharkar

Venugopal Kolathur

Parag Naik

Deepanjan Kar

Srivatsan Raghavan

Ragesh Thottathil Ramachandran

Someshwar Dk

Sangamesh O Shetty

Shrinivas Nagaraddi

A method for operating a hardware-software interface (HSI) executable specification unit by means of an executable hardware-software interface (HSI) specification for a computing device is provided. The executable HSI specification is a form of a Device Programming Specification (DPS). The HSI executable specification unit includes a HSI analyser, at least one skeletal driver and a HSI executable specification interpreter. The method includes (i) capturing at least one HSI for generating the executable HSI specification, (ii) analyzing at least one section of the DPS to determine sequences that are required for executing the executable HSI specification, (iii) parsing, using the HSI analyzer, the DPS into an intermediate form, (iv) verifying if an intermediate representation (IR) for each of the sequences to be invoked in at least one skeletal driver Application Programming Interface (API) is present and (v) translating the sequences of the DPS into at least one hardware-software interface (HSI) intermediate representation (IR).

System and method for generating an executable hardware-software interface specification

A processor-implemented method for transforming co-routines to equivalent sub-routines is provided. An input is received at a first user device from a user for a first language and a first operating environment. The first language includes the co-routines and is supported in a first hardware environment. The first language is analyzed to transform the co-routines of the first language into the sub-routines of a second language for implementing the co-routines of the first language in a second hardware environment. The second hardware environment supports the sub-routines of the second language in a second operating environment by determining automatic variables for persistent variables and non-persistent variables, transforming the persistent variables and the non-persistent variables into the sub-routines of the second language, determining return statements and yield statements in the co-routines, and translating the co-routines of the first language into the sub-routines of the second language and the second operating environment.

System and method for transforming co-routines to equivalent sub-routines

A system and method for automatically generating device driver codes for a device model based on an operation of said device model in verification environments is provided. The System includes a computing device. The computing device includes a device programming specification receiving module, a run time specification parsing module, a verification environment determination module and a driver generation module. The device programming specification receiving module receives at least one device programming specification aspects associated with an operation of device model in verification environment to determine a type of device driver code to be generated. The run time specification parsing module parses a run time specification file that includes verification environment parameters in run time specification. The verification environment determination module determines whether the verification environment equals to a part of a simulation/emulation in run time specification. The driver generation module automatically generates device driver code in pre-determined output programming language.

System and method for automatically generating device drivers for run time environments

A computer-implemented verification system for performing a system level or a system on chip level functional verification of integrated circuit is provided. The computer-implemented system includes one or more processors and a memory storing instructions defined by one or more modules of including a scenario compiler, a verification component and a software library component. The scenario compiler receives a set of verification scenario intents including at least one of test-application intents, constraints, device-programming intents and scenario-control intents. The scenario compiler generates one or more open verification methodology (OVM) and/or universal verification methodology (UVM) compliant test bench sequences and one or more scenario software implementations based on the set of verification scenario intents. The verification component interacts with the integrated circuit using the OVM and/or UVM compliant test bench sequences. The software library component enables execution of the scenario software implementations on a processing unit core of the integrated circuit.

Computer-implemented verification system for performing a functional verification of an integrated circuit

A system for validating a hardware platform is provided. The system includes a database that stores one or more test specifications, a compiler that generates a target image based on (i) a device driver obtained from a device driver generator, (ii) a platform independent target application code, (iii) a kernel source, and (iv) a run time environment, and a software driven validation generator that analyzes the run time specification and the device programming specification and generates (i) one or more test cases based on (a) the one or more test specifications, and (b) the device programming specification, and (ii) a control software based on the test cases. The test cases include configurations that are specific to the hardware platform. The hardware platform is validated based on (i) an execution of the target image and the control software on the hardware platform, and (ii) the one or more test cases.

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Bengaluru, India

Karthick Gururaj