Intel Corporation

Karthi R Vadivelu

Satheesh Chellappan

Mikal Hunsaker

Huimin Chen

Darren L Abramson

Abdul Rahman Ismail

Anoop Mukker

Sridharan Ranganathan

Raul N Gutierrez

Michael N Derr

David J Harriman

David I Poisner

Amit Kumar Srivastava

Chia-Hung Sophia Kuo

Zhenyu Zhu

Alberto J Martinez

Kar Leong Wong

Choon Gun Por

David Hines

Zeeshan Sarwar

Shalini Sharma

Bryan C Doucette

Prashant Sethi

Nitin V Sarangdhar

Nausheen Ansari

Robert E Gough

Andrew W Martwick

Steven Bernard McGowan

Howard L Heck

Joseph A Bennett

John S Howard

Ajay V Bhatt

Karunakara Kotary

Peter S Adamson

Kenneth Foust

Nivedita Aggarwal

Reuven Rozic

Kok Hong Chan

Tin-Cheung Kung

Pronay Dutta

Rajesh Bhaskar

Adeel A Aslam

Yong Yang

Vijay S R Degalahal

Panner Kumar

Kian Leong Phang

Shanthanand R Kutuva

Rahul Bhatt

Described is an apparatus comprising a first interface, a second interface, a third interface, and an interconnection fabric. The first interface may transfer a first stream of data traffic. The second interface, which may be an enhanced Serial Peripheral Interface (eSPI) interface, may transfer a second stream of data traffic and a third stream of data traffic. The third interface may transfer a fourth stream of data traffic. The interconnection fabric may couple the first interface to the second interface and may couple the second interface to the third interface. The second interface may initiate a transfer of an outbound data stream from one of the second stream of data traffic or the third stream of data traffic based on an available-space credit indicator. The second interface may receive an inbound data stream based upon the outbound data stream.

Low power data processing offload using external platform component

Embodiments of the present disclosure are directed toward a universal serial bus (USB) device and a USB host controller. The USB device and USB host controller may be configured to couple to one another via a USB link that may include a high-speed data line and a low-speed data line. The USB device may then transmit, via the high-speed data line, an indication of a digital image to the USB host controller. Other embodiments may be described and/or claimed.

High bandwidth universal serial bus (USB) camera

Apparatuses relating to periodic Universal Serial Bus (USB) transaction scheduling at fractional bus intervals are described. In one embodiment, an apparatus includes a receptacle to receive a plug of a first device and a second device; a transceiver circuit coupled to the receptacle; and a controller circuit to: switch between a first mode for a first class of data transfers and a second mode for a second class of data transfers, wherein the first class preempts the second class of data transfers, schedule a data transfer with the transceiver circuit for a first endpoint of the first device at a first service interval of a bus interval when in the first mode, and schedule a data transfer with the transceiver circuit for a second, different endpoint of the second device at a second service interval that is smaller than the first service interval when in the first mode.

Apparatuses for periodic universal serial bus (USB) transaction scheduling at fractional bus intervals

An apparatus to transfer data via a communication link comprises a power bus interface to a power bus of the communication link; at least one data lane transmitter and receiver pair configured to transfer data via a data lane of the communication link; and a power bus data transmitter and receiver pair configured to transfer data via the power bus using pulse width modulation of a data signal on the power bus.

Mechanism of power delivery on an asymmetrical dual simplex link

In one embodiment, a flash sharing controller is to enable a plurality of components of a platform to share a flash memory. The flash sharing controller may include: a flash sharing class layer including a configuration controller to configure the plurality of components to be flash master devices and configure a flash sharing slave device for the flash memory; and a physical layer coupled to the flash sharing class layer to communicate with the plurality of components via a bus. Other embodiments are described and claimed.

System, apparatus and method for sharing a flash device among multiple masters of a computing platform

Embodiments may include systems and methods for communication including a plurality of controllers and coordination circuitry, to control communication to or from an interface circuitry. The interface circuitry includes a plurality of pins, where a first group of pins of the plurality of pins is for a first communication protocol, and a second group of pins of the plurality of pins is for a second communication protocol. A first controller is coupled to the interface circuitry through the first group of pins, and a second controller is coupled to the interface circuitry through the second group of pins. The coordination circuitry is to select the first controller or the second controller to control communication to or from the interface circuitry. Other embodiments may be described and/or claimed.

Selective connection for interface circuitry

In one embodiment, a system on chip includes: at least one core; a plurality of intellectual property (IP) agents coupled to the at least one core; a shared power rail to provide an operating voltage to the plurality of IP agents; and a power controller, in response to an indication that the plurality of IP agents are in an idle state and the at least one core is in an active state, to power down the shared power rail while the at least one core remains in the active state. Other embodiments are described and claimed.

System, apparatus and method for collective power control of multiple intellectual property agents and a shared power rail

Particular embodiments described herein provide for an electronic device that can receive data from an operating system in an electronic device, where the data is related to hardware that is in communication with the electronic device through a multimodal interface and communicate the data and/or related data to a local policy manager, where the local policy manager is in communication with the multimodal interface. The multimodal interface can be configured to support power transfers, directionality, and multiple input/output (I/O) protocols on the same interface.

Multimodal interface

An example includes an apparatus for transmitting Universal Serial Bus (USB) packets. The apparatus includes a transmitter adapter to receive a USB packet from a USB device. The transmitter adapter can further generate one or more alternate mode packets based on the USB packet. The transmitter adapter can also transmit the alternate mode packets via an alternate mode connection.

Transmitting universal serial bus (USB) data over alternate mode connection

An example apparatus includes: a host controller offload capability detector to determine that a media stream offload capability is available in the peripheral interface host controller; a media stream offload arbiter to send a media stream offload request to a media processor manager based on the media stream offload capability and based on a peripheral device being connected to the peripheral interface host controller; and an endpoint mapper to generate an endpoint table entry corresponding to the peripheral device, the endpoint table entry to assign a first communication interface of the peripheral interface host controller to transfer a media stream corresponding to the peripheral device between the media processor and the peripheral interface host controller without the media stream being routed to an application processor that is in circuit with the peripheral interface host controller and in circuit with the media processor.

Methods and apparatus to offload media streams in host devices

An apparatus is described herein. The apparatus includes a Universal Serial Bus (USB) component and a controller interface. The controller interface is to allocate register space for interfacing with the USB component and the USB component is virtualized into multiple instantiations. The apparatus also includes a secure environment, and the secure environment further virtualizes the multiple instantiations such that the multiple instantiations are owned by the secure environment.

Additional secured execution environment with SR-IOV and xHCI-IOV

In one embodiment an electronic device includes a processor and at least one universal serial bus (USB) subsystem comprising logic, at least partially including hardware logic, configured to detect a connection from a remote electronic device to a USB port of the electronic device, determine whether the USB port of the electronic device is to act as an upstream facing port or a downstream facing port, and in response to a determination that the USB port of the electronic device is to be configured as an upstream facing port, to implement a port mapping process to map the USB port to one of a device controller or a debug controller. Other embodiments may be described.

System and method for universal serial bus (USB) protocol debugging

An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB3.0 system interface and an M-PHY interface, wherein the SSIC is configured to issue remote register access protocol (RRAP) commands through a local M-PHY to a remote M-PHY in a low speed burst mode.

Configuring a remote M-PHY

Techniques for reducing idle power consumption of a port are described herein. An example method includes determining device presence using a pull-down resistor disposed in a downstream port. The method also includes initiating a low power state of a link between the downstream port and an upstream device. The method also includes disabling the pull-down resistor in response to initiating the low power state.

Reduction of idle power in a communication port

The present techniques include detecting a charger and remote host for a Type-C connector. An apparatus, system, and method are described herein. The apparatus comprises a USB Type-C port and a USB receiver detector. A charger and a remote host are differentiated based on the USB receiver detector.

System to detect charger and remote host for type-C connector

Growing community of inventors

Folsom, CA, United States of America

Karthi R Vadivelu