Rambus Inc.

Oracle International Corporation

Adaptive Media Technologies

Karnamadakala Krishnamohan

Jeyendran Balakrishnan

Kowsik Guruswamy

Devendra Kalra

Timothy J Burr

Venkatasubbarao Ramamoorthy

Frederick Abbott Ware

Craig Edward Hampel

Michael P Farmwald

Paul G Davis

James A Gasbarro

John Bradly Dillon

Pradeep Batra

Paul Michael Farmwald

The present invention provides an apparatus and method for encoding, storing, transmitting and decoding multimedia information in the form of scalable, streamed digital data. A base stream containing basic informational content and subsequent streams containing additive informational content are initially created from standard digital multimedia data by a transcoder. Client computers, each of which may have different configurations and capabilities are capable of accessing a stream server that contains the scalable streamed digital data. Each different client computer, therefore, may access different stream combinations according to a profile associated with each different client computer. Thus, the streams accessed from the server are tailored to match the profile of each client computer so that the best combination of streams can be provided to maximize the resolution of the 3D, audio and video components.

Method and apparatus for storing base and additive streams of video

Method and apparatus that provides a scalable media delivery system

In a system comprising a current controlling device and a plurality of signal lines coupled to the current controlling device, wherein the current controlling device has an output driver including a register, an improved method for setting a current of the output driver for at least one of the plurality of signal lines. The improved method determines a reference register-setting for the register of the current controlling device. The reference register-setting corresponds to a reference voltage for at least one of the plurality of signal lines. A target register-setting is then determined for the register based on the reference register-setting. The target register-setting corresponds to a target voltage for at least one of the plurality of signal lines, wherein the target voltage produces an appropriate swing about the reference voltage. An operational register-setting is then determined for the register based on the target register-setting. The current of the output driver for at least one of the plurality of signal lines is then set based on the operational register-setting so that a swing about the reference voltage is optimal.

Method and apparatus for setting a current of an output driver for the

A cache system which includes prefetch pointer fields for identifying lines of memory to prefetch thereby minimizing the occurrence of cache misses. This cache structure and method for implementing the same takes advantage of the previous execution history of the processor and the locality of reference exhibited by the requested addresses. In particular, each cache line contains a prefetch pointer field which contains a pointer to a line in memory to be prefetched and placed in the cache. By prefetching specified lines of data with temporal locality to the lines of data containing the prefetch pointers the number of cache misses is minimized.

Cache system and method for prefetching of data

A cache subsystem for a computer system having a processor and a main memory is described. The cache subsystem includes a prefetch buffer coupled to the processor and the main memory. The prefetch buffer stores a first data prefetched from the main memory in accordance with a predicted address for a next memory fetch by the processor. The predicted address is based upon an address for a last memory fetch from the processor. A main cache is coupled to the processor and the main memory. The main cache is not coupled to the prefetch buffer and does not receive data from the prefetch buffer. The main cache stores a second data fetched from the main memory in accordance with the address for the last memory fetch by the processor only if the address for the last memory fetch is an unpredictable address. The address for the last memory fetch is the unpredictable address if both of the prefetch buffer and the main cache do not contain the address and the second data associated with the address.

Prefetching into a cache to minimize main memory access time and cache

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San Jose, CA, United States of America

Karnamadakala Krishnamohan