Siemens Aktiengesellschaft

Karlheinz Krause

Majid Ghameshlu

Elke Tiemeyer

Johann Deix

In order to program a memory module, some of its inputs are stimulated via internal memory locations of a so-called boundary scan (BSCAN) register that is provided in the form of an IC or ASIC. In order to activate or deactivate a write operation, the control signal input of the memory module, said control signal input being responsible for generating a WRITE_ENABLE signal, is controlled exclusively. The switching over of the WRITE_ENABLE signal from 'LOW' to 'HIGH' potential and vice versa thus ensues according to two JTAG instructions of an instruction sequence that provides for the generation of a LOW or HIGH level at the setting signal input or resetting signal input of an update flip-flop of the memory location responsible for generating the WRITE_ENABLE signal. By appropriately modifying the control unit and the BSCAN cell, which stimulates the WRITE_ENABLE signal at the WR input of the memory module, the programming can be accelerated without having to expand the interface between the control unit and the BSCAN register to the board and equipment level. In another embodiment of the invention, a control unit automatically switches over the WRITE_ENABLE signal from &#x201c;LOW&#x201d; to &#x201c;HIGH&#x201d; potential or from HIGH to LOW potential at an appropriate or rather programmable point in time by setting or resetting the update flip-flop of the memory location responsible for generating the WRITE_ENABLE signal.

Acceleration of the programming of a memory module with the aid of a boundary scan (BSCAN) register

A method and parallel interface for on-board programming and/or In-System Configuration of a flash memory mounted on a printed circuit board by controlling its inputs with the aid of an ASIC mounted on the same circuit board via a Boundary Scan register of which the output signals are provided for activating or deactivating a write operation. The architecture description of the ASIC, flash memory, and the data format of the program and configuration data are stored in a Boundary-Scan Description Language file. The circuit board can be controlled via a JTAG interface suitable for performing function testing of the flash memory for input or output of standard bus signals and for input of the control signals of the ASIC. To reduce the programming effort, the data of the circuit diagram or of the network list derived from it is stored in the BSDL file.

Programming flash memory via a boundary scan register

An IC including duplicated primary components which can be operated microsynchronously has at least one synchronization device for synchronizing asynchronous signals to the primary clock. An asynchronous signal intended for the primary components is routed via the synchronization device, synchronized and supplied to the inputs of the primary components. With duplicated asynchronous components, an output signal from just one asynchronous component is synchronized and is supplied to the primary components.

Integrated circuit including duplicated synchronous and asynchronous components

The present invention, in addition to the number of connections required for the specified functions of an ASIC, provides an application specific module ASIC that has additional connections as spares for subsequent modification. Buffers, boundary scan devices and, possibly, basic logic function, are reserved for the additional connections, which may be arranged in a geometrically uniform distribution and which are intended as inputs or as outputs. In the event of a redesign, in particular in the event of only minor design corrections, the effort development costs and time is considerably reduced.

Low redesign application-specific module

An integrated circuit having at least two clock systems in which the appropriate clock signal, starting from a clock input, can be forwarded through clock trees to individual switching elements or switching blocks. In this arrangement, each clock tree has an associated controlled switch which, for selected operating states, can be used to apply a single common clock signal to the clock trees, where at least a first clock tree has a PLL unit connected upstream of it, and an output of this clock tree is connected to an input of the PLL unit in order to form a phase locked loop, and the switches are actuated in selected operating states such that the common clock signal is supplied to a last clock tree, and an output of this clock tree is connected to the other input of the PLL unit for the at least first clock tree.

Integrated circuit comprising at least two clock systems

An integrated electronic module which is equipped with at least one hardware error infeed for testing purposes and which includes a number of terminals whereby the error infeed is controlled with a control logic. The control logic includes at least one terminal as data input for command signals at the control logic as well as an error control output which is connected to a signal input of the error infeed. The control logic decodes the command signals entered via the data input, derives commands for error control therefrom and gives signals to the error control output corresponding to these commands. The control logic may be constructed as part of a boundary scan test logic of the module.

Growing community of inventors

Planegg, Germany

Karlheinz Krause