Siemens Aktiengesellschaft

Karlheinrich Horninger

Karl-Ulrich Stein

Guenther Meusburger

Lothar Schrader

Heinz-Peter Holzapfel

Three-value modulo-2-adders consist of four circuit components (SC1, SC2, SC3, SC4) and an analysis circuit (AW). The first circuit component (SC1) generates an intermediate signal corresponding to the first binary value ('1') when two of the input signals (A, B, C) each assume the other binary value ('0'). The second circuit component (SC2) generates an intermediate signal (ZS2) corresponding to the other binary value when two input signals each assume the first binary value. The intermediate value emitted from the output of the third circuit component (SC3) is binary '0' when all three input signals assume the binary value '1'. The fourth circuit component (SC4) emits the binary value '1' when all the input signals have the binary value '0'. The analysis circuit (AW1) switches through the first or second intermediate signal to the output when the third intermediate signal has the value binary '1' and the fourth intermediate signal has the value binary '0', otherwise the third or fourth intermediate signal is switched through in inverted form to the output.

Modulo-2-adder for the logic-linking of three input signals

A driver stage formed in integrated MOS technology has a large output signal ratio but with reduced idle currents. First and second control stages are provided of MOSFETs series connected and with their outputs between the MOSFETs connecting to respective gates of an output stage also comprised of series connected MOSFETs. In the output stage, one of the MOSFETs has its channel resistance reduced and is parallel-connected with an additional MOSFET. A boot strap capacitor connects between a gate of the additional MOSFET and an output of the circuit.

Integrated MOS driver stage with a large output signal ratio

A monolithically integrated semiconductor arrangement is disclosed wherein a plurality of first lines are provided which run parallel to one another and which are provided with first terminals at one end. A plurality of second lines which run parallel to one another are also provided which cross beneath the first lines and are connected via load elements at one end to a supply voltage terminal. Reference potential lines are also provided adjacent each of the second lines. At a series of selected crossing points of the first and second lines coupling elements are formed which can be operated by the first line and by which the second line is connected to an adjacent reference potential line. The semiconductor arrangement is formed on a semiconductor layer having a thin insulating layer thereon with the second lines and reference potential lines arranged on the thin insulating layer. The first lines are then arranged over the second line and reference potential lines and are separated therefrom by an additional insulating layer. At crossing points selected for coupling, a portion of the first line approaches the semiconductor layer surface more closely and is separated therefrom by the thin insulating line. Diffusion zones are provided at one end of each of the reference potential lines and second lines. With the system disclosed, diffusions are not required for the formation of the first and second lines and coupling elements.

Monolithically integrated semiconductor arrangement

A monolithic integrated circuit arrangement is disclosed which is formed of a group of one-transistor storage elements arranged on a semiconductor layer. Each storage element has a selection field effect transistor and a storage capacitor. The storage elements are arranged in pairs. First and second storage capacitors of each pair are combined to save storage area. In one embodiment, a first conductive coating overlying a surface of the semiconductor layer is employed as a common second electrode for all the storage capacitors. Additional second conductive coatings insulated from the first conductive coating and arranged thereover form the first electrodes for the storage capacitors. In another embodiment a first conductive coating is employed as a common second electrode for the storage capacitors. A second conductive coating is utilized as a first electrode for some of the storage electrodes while an inversion or diffusion layer is utilized as a first electrode for the other storage capacitors. In a final embodiment a first conductive coating over the semiconductor layer is utilized as a common second electrode for all of the storage capacitors. A second conductive coating over the first conductive coating and insulated therefrom is utilized as a first electrode for some of the storage capacitors whereas other storage capacitors have their first electrode formed as an inversion layer adjacent to a shift electrode.

Monolithically integrated circuit arrangement comprising one-transistor

A field effect transistor having an extremely short channel length in which a semiconductor substrate of one conductivity type has source and drain zones of the opposite conductivity type. A first gate electrode is separated from the substrate surface by a first insulating layer. The substrate has a surface side counter zone doping extending between the source and drain with the exception of a narrow strip-like zone which directly adjoins the source. The strip-like zone and at least an adjoining part of the surface side counter doped zone is covered by the first gate electrode. A second insulating layer is formed on the first gate electrode and on the drain side edge face of the first gate electrode. A coating on the second insulating layer covering that portion of the first insulating layer not covered by the first gate electrode is formed. The source side edge of the coating determines the drain side boundary of the strip-like zone. The source side edge of the first gate electrode determines the source side boundary of the strip-like semiconductor zone. The first gate electrode is connectable to a control voltage.

Field effect transistor having an extremely short channel length

A linear output amplifier for a charge coupled device arrangement in which the amplifier has a field effect switching transistor serially connected to a load element, the connection point between the transistor and the load element being the output of the amplifier and the gate terminal of the transistor being the input of the amplifier. The input of the amplifier is connected to the charge coupled device arrangement by either connecting it to the output diffusion zone of the same or by connecting it to a control electrode of the charge coupled device arrangement. Between the output of the amplifier and the input of the amplifier an additional transistor is provided with the aid of which the input can be connected to the output. Preferably, the load element is a field effect transistor and the load resistance which it provides can be varied by connecting a voltage source of desired amplitude to the gate terminal thereof.

Linear output amplifier for charge-coupled devices

The invention relates to a dynamic single-transistor memory element whereby the information may be stored for long periods of time without an energy supply. The invention also provides for a dynamic single-transistor memory element having the capability of storing two differing information pulses. The write-in process may be effectuated element-wise, line-wise, or matrix-wise. The invention further provides the capability to effectuate the erasure of the information line by line where the information is intermedially stored in the regenerator amplifiers or matrix by matrix where the intermediate storage occurs in the second matrix.

Dynamic single-transistor memory element for relatively permanent

An integrated programmable logic arrangement is provided into which a logic pattern can be electronically written, and out of which a logic pattern can be electronically read-out. The logic arrangement has an AND-matrix, an OR-matrix, switching transistors in the AND and OR matrices comprising MI.sub.1 I.sub.2 S (metal-insulation 1-insulation 2-semiconductor) storage type transistors, and decoder means connected to the AND and OR matrices.

Integrated programmable logic arrangement

A phase comparator has at least two signal comparison inputs and at least one resistance line and one or more voltage amplitude comparators. A first comparator input of each voltage amplitude comparator is connected to the resistance line. One end of the resistance line is connected by way of a first dc voltage blocking means to the first signal comparison input and the second signal comparison input is connected by way of an inverter and a second dc voltage blocking means to the other end of the resistance line. In one mode of operation the one end of the resistance line is connected to a fixed voltage and the other end is connected to an impressed current source, and the second comparator inputs of all the voltage amplitude comparators are connected to a fixed reference voltage which is equal to the arithmetic mean of the two voltages present at the ends of the resistance line and produced by the current source and the voltage source. In this mode of operation each signal comparison input is fed with one of two input signals which are to be compared and the output signal of the phase comparator is provided in parallel from all of the comparator outputs. In another mode of operation, one end of the resistance line is connected to a fixed voltage and the other end is connected to an impressed current source. The second comparator input of all the voltage amplitude comparators are connected to a fixed reference voltage which is equal to the arithmetic mean of the two voltages present at the ends of the resistance line and produced by the fixed voltage and the impressed current source. The two ends of a second resistance line are connected to a fixed voltage and a further resistor has one end connected to a tap of the second resistance line and another end connected to a fixed voltage. In this mode of operation each signal comparison input is fed, in each case, with one of the two input signals which are to be compared and the output signal of the phase comparator is obtained at the tap of the second resistance line.

Phase comparator and process for the operation thereof

An integrated circuit comprising a programmable logic array includes an AND-gate array and an OR-gate array connected thereto with column lines of the AND-gate array being shared in common with column lines of the OR-gate array. The AND-gate array and the OR-gate array are both operated dynamically, and a dynamically operated shift register is interconnected between an output of the OR-gate array and an input of the AND-gate array, to supply a feedback signal to the latter to realize sequential logic functions.

Integrated programmable logic array

A dynamic storage element is characterized in that, in addition to the transistors of the storage element, at least one MI.sub.1 I.sub.2 S storage transistor is provided to receive the data stored in the storage element. The dynamic storage element comprises a transistor and a series-connected capacitor. The transistor is connected on the one hand to the capacitor and on the other hand to a bit line, and the gate terminal of the transistor is connected to a word line. In particular, a MI.sub.1 I.sub.2 S storage transistor is additionally provided which is connected on the one hand to the word line and on the other hand to a point at which the transistor and the capacitor are connected in series and the gate terminal of the MI.sub.1 I.sub.2 S storage transistor is connected to a gate line.

Dynamic transistor-storage element

An MNOS transistor for electric information storage circuits includes one channel and has a layered gate insulator. A plurality of such MNOS transistors are arranged in a matrix on the substrate and the start voltage is variably dependent upon the electric charge stored in the gate insulator of each transistor. The channel length of the MNOS transistor is shorter than twice the depletion layer thickness during recording or erasure of data, and during recording of data and during read-out and erasure of data only voltages of the same polarity are applied between the gate, source, and drain electrodes and the common substrate.

Information storage circuit employing MNOS transistors

An associative storage circuit characterized in that a storage cell therefor includes two circuit arms in parallel, each arm having one MNOS storage transistor and one switching transitor connected in series, and that the information which is to be written in, and the comparison information during readout, may be applied to the gates of the switching transistors, the storage transistors in one embodiment having a common gate line; in a second embodiment having individual gate controls for bit-by-bit write-in of information; and in a third embodiment, having a common gate line and a common substrate terminal line with bit-by-bit write-in by means of opposite polarity write-in potentials.

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Eglharting, Germany

Karlheinrich Horninger