International Business Machines Corporation

Karl V Swanke

Mark J Flemming

Sebastian Theodore Ventrone

John Maxwell Cohn

John Chester Malinowski

Michael Richard Ouellette

Riyon W Harding

Shawn M Luke

Alexander Joseph Franz

Raghav Kohli

Matthew S Turnbull

Tyler D Kieft

Matthew Walker

Disclosed are an object locator system, a method and a program storage device. In the embodiments, radio frequency identification (RFID) tags are on objects within a defined area and each RFID tag can be activated by an RF activation signal. When a request (e.g., a verbal or keyed-in request) to locate a specific object is received from a specific user, the required permission to locate the object is verified and, optionally, the identity of the specific user is authenticated. Once the required permission is verified and the identity of the specific user is authenticated, one of three RFID readers transmits an RF activation signal. RF response signals received back at the three RFID readers from the specific object's RFID tag are used to triangulate the position of the specific object. Once determined, the position is communicated (e.g., by map display, verbal message, or text message) to the specific user.

Security-enhanced radio frequency object locator system, method and program storage device

Methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification used to fabricate the die and a product chip location for the die on a wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.

Methods for reading a feature pattern from a packaged die

Product chips and die that include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification used to fabricate the die and a product chip location for the die on a wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.

Product chips and die with a feature pattern that contains information relating to the product chip

A tool and method is provided to graphically correlate process and test data with specific chips on a multi-project wafer. The tool and method is configured and implemented to select certain sites and export these sites to an industry standard map that can be used in a variety of chip picking or test tools. In one embodiment, the method includes importing a wafer floor plan with chips of different design parameters and importing manufacturing logistical information of the chips. The method further includes graphically rendering each chip on the wafer to scale within a unit cell using the imported wafer floor plan and the manufacturing logistical information.

Tool and method to graphically correlate process and test data with specific chips on a wafer

Product chips and die, methods for fabricating product chips, and methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification for a wafer used to fabricate the die and a product chip location for the die on the wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.

Fabricating product chips and die with a feature pattern that contains information relating to the product chip

A method and structure for coordinating resources to complete a design project prioritizes tasks to create a project plan, automatically notifies resources of task responsibilities and associated due dates based on the project plan through the use of encryption keys, controls access to the design data through the use of the encryption keys assigned to the resources, automatically monitors work being performed on tasks through a computerized network, and automatically notifies a project team leader of task completion status, overdue tasks, and tasks being ignored, based on the monitoring.

System and method for planning a design project, coordinating project resources and tools and monitoring project progress

A random number generator () comprising a plurality of voltage islands () on a chip (), one or more latches () located on each of plurality of voltage islands (), with one or more latches () adapted to capture the voltage value of the respective voltage island on which they are located as an input value of one or more latches (), a control circuit () for randomly controlling the state of each of plurality of voltage islands () and for capturing an output value for each of one or more latches (), and a conversion circuit () for producing decimal numbers from the output value for each of one or more latches (). In one embodiment, control circuit () includes two or more clocks (), a multiplexer () for each of plurality of voltage islands (), and an enable circuit () for each of plurality of voltage islands ().

Growing community of inventors

Essex Junction, VT, United States of America

Karl V Swanke