Cirrus Logic Inc.

Avocent Huntsville Corporation

Vertiv It Systems, Inc.

Karl Scott Mills

Richard Charles Owen

Mark Emil Bonnelycke

Jeffrey Michael Holmes

Bradley A May

Phillip R Kent

Lawrence Lo

Lauren Emory Linstad

Vernon Dennis Hasz

Brian Alfred Williams

Steven Geffin

Yang Pu

Sherwood Brannon

Jedd Perry

John Reed

Bharat A Khuti

Donald A Sturgeon

James H Shelton

Aman Khan

Jack Basiago

Kenneth Lee Harper

Steven R Blackwell

Roy Pestone

Steven Clark

Richard M Tobin

Dai Jun

Phil Kent

James Pursel

Sheldon Altman

Luis Reyes

Bob Seifert

Juarez Carvalho

Jeff Fore

Wes Wirth

Doug Collins

Michael Browner

John Hoskyn

Edwin Wong

Mitesh Patel

Mike Straub

Keith Schuettpelz

Richard Charles Andrew Owen

James R Mataya

David John Cowen

Mark Kershner

Mark Emill Bonnelycke

Christopher R Hinshaw

Jean-Maxime Lachapelle

Adam W Lew

Richard Williams

Mehmood Nurmohamed

Joe Kutner

A backup power system is disclosed which has a first port in communication with a server. The server includes first and second ports, and the backup power system is in communication with the second port of the server and receives a first voltage signal from the second port of the server. A second communications port of the system is in communication with a peripheral. The peripheral is powered by a separate connection to the first port of the server. A controller of the system detects when power being provided by the server through the server's second port has dropped below a threshold level. A power storage component responsive to the controller supplies power to the peripheral when the power provided from the server's second port drops below the threshold level.

Dongle having rechargeable, supercapacitor based power supply

The present disclosure relates to a system and method for enabling implementation of a secondary function of a universal serial bus (USB) device on a computer that the USB device is communicating with, wherein an operating system of the computer does not have a required driver which needs to be mapped to the USB device to enable implementation of the secondary function. The system involves a USB device which has the required driver for implementing the secondary function stored therein. The required driver can be supplied to the computer from the USB device using a control which selects the secondary function of the USB device.

System and method for presenting driver install files when enabling a USB device

A system for monitoring, controlling and optimizing power usage and cooling utilization within a data center infrastructure. The system may make use of a subsystem which is adapted to obtain real time information on both facility devices and information technology (IT) devices. The subsystem may be used to evaluate the real time information to provide an alert and diagnostic information with respect to at least one of the facility devices or at least one of the IT devices. The subsystem may also make use of a mechanism that provides real time control over at least one of the facility devices or at least one of the IT devices to optimize at least one of cooling utilization, power usage or performance of at least one of the facility devices or at least one of the IT devices.

System and method for monitoring and managing data center resources in real time

A digital rack interface pod (DRIP) that is able to establish a communications link between a remote access appliance and a server having a USB port and a video port, to facilitate a keyboard/video/mouse (KVM) session between the server and the appliance. The DRIP is also able to establish a communications link between the appliance and an Ethernet port of the server that is associated with a service processor (SP) of the server. In this manner the DRIP is able to route data from the SP of the server to the appliance as well as communications from the appliance to the SP Ethernet port of the server. The DRIP is able to intelligently determine which packets of information received from the appliance are intended for the SP Ethernet port of the server and routes those packets to the SP Ethernet port of the server. The DRIP also automatically monitors and dynamically reassigns its two Ethernet ports as needed so that whichever one of its two Ethernet ports it discovers a connection with the appliance on will be the port that it continues using to communicate with the appliance.

Digital rack interface pod system and method

An intelligent power control system and method adapted for use with a digital rack interface pod (DRIP). A switching regulator generates a set output voltage. If power is available from a USB port of an external device, such as an external server, then the system uses this power to power the DRIP. If DC power is detected as being received on a different input from an external power transformer, then the system may still continue to use the power being received from the USB port to power the DRIP. If power from the USB port of the external device is lost but power from the external transformer is present, then the system may use the power available from the external transformer to power the DRIP. If the DRIP is being powered by USB power from the external device, and no DC power is available from the external transformer, but backup power from an appliance to which the DRIP is coupled is being received on one of the DRIP's power input ports, then the DRIP may switch to backup power from the appliance if power from the USB port of the external device (e.g., server) is lost. The system thus intelligently prioritizes the use of power available from a plurality of different power sources to maintain the DRIP powered on when one or more of the power sources is lost or otherwise not available.

Digital rack interface pod (DRIP) with intelligent power control system and method

A high definition video transmitter and receiver are disclosed. The transmitter provides high definition video to a one-point receiver or to multipoint receivers. The transmission network is asynchronous and the receiver re-synchronizes the video. The transmission can be wired or wireless.

Point-to-multipoint high definition multimedia transmitter and receiver

A graphics controller circuit for minimizing an amount of data received from a host. The graphics controller circuit includes a register file with a plurality of registers. The graphics controller accepts commands addressed to virtual registers, and generates plurality of instructions including an instruction to access one of the registers in the register file. By using such a virtual register number in a command and generating several instructions in response thereto, the graphics controller circuit of the present invention minimizes the amount of data host sends over the system bus.

Method and apparatus for executing commands in a graphics controller chip

The present invention discloses methods and apparatus for implementing automatic graphics operations with selectable triggering mechanism. One mechanism is hardware related, using the vertical counter in the video control section of the graphics processor. The other mechanism is software related, using the host to directly command the graphics processor. The graphics operations are specified in the header file written by the host in the frame buffer memory. Several header files can be chained together to form a sequence of header files corresponding to very complex graphics operations. Automatic graphics operations, therefore, can be completed without further host intervention resulting in powerful graphics, video, and animation performance.

Integrated graphics processor having a block transfer engine for

A graphics controller circuit comprising a plurality of pipelines for performing a set of operations on a stream of input pixel data to generate at least a first operand and a second operand. A rasterop unit in the graphics controller circuit may receive the first operand and the second operand, and execute a raster operation using the first operand and the second operand to generate a set of display pixel data. The graphics controller circuit may further comprise a transparency unit for generating a write enable mask corresponding to the set of display pixel data. A display memory may selectively store or block the set of display pixel data according to the write enable mask. As the graphics controller generates display signals from the display data stored in display memory, a transparency operation may be performed.

Method and apparatus for executing a raster operation in a graphics

A method and apparatus for determining representative values for the chrominance components to be associated with a plurality of luminance components in a horizontally shrunken or stretched image for graphics controllers wherein display image data is stored in a buffer memory in a form associating a single set of U and V chrominance components with a plurality of Y luminance values. For a four to one shrinkage of an image in a format associating one set of chrominance components with four pixel luminance values wherein each pixel luminance value in the shrunken image initially has as associated set of chrominance components U.sub.0, U.sub.1, U.sub.2 and U.sub.3 and V.sub.0, V.sub.1, V.sub.2 and V.sub.3, the multiple values of the chrominance components are sequentially accumulated in a 3/4:1/4 ratio in such a manner as to provide an approximate average value for U and V for each set of four pixel luminance values in the shrunken image. Circuitry for processing the chrominance components making use of interpolation circuitry already used for interpolation between pixels for a stretched image is disclosed.

Method and apparatus for determining representative chrominance

A graphics controller circuit for converting a plurality of monochrome pixel data into a corresponding set of color pixel data in RGB 888 format. The graphics controller circuit packs the converted color pixel data into a plurality of 64-bit color pixel words, with each color pixel word comprising two complete color pixel words and portion of at least one another color pixel word. By having color pixel data cross word boundaries, graphics controller of the present invention optimally stores color pixel data in color pixel words. The graphics controller circuit further includes a half-word addressable split-RAM which enables continuous availability of subsets of monochrome pixel data during each clock cycle for conversion to color data.

Method and apparatus for converting monochrome pixel data to color pixel

A method and apparatus for improving pixel data write operations to a tile-based frame buffer. The present invention includes a byte enable first-in first-out register for storing byte enable data for masking pixel data writes to a tile based frame buffer when the pixel data crosses a tile boundary. Pixel data generated by a graphics processor to the frame buffer may traverse multiple tiles. With each 64-bits of pixel data generated, a corresponding byte of byte enable data is generated as mask data for the frame buffer. The byte enable circuit of the present invention may be implemented as a circular shift register to allow the byte enable data to be shifted, rather than being 'popped' after the pixel data has been written to the frame buffer. By shifting data rather than 'popping' data, the byte enable circuit is able to retain portions of the byte enable data to enable a correct write of a pixel word which may traverse tile boundaries.

Method and apparatus for optimizing pixel data write operations to a

A transaction queue for transferring data between a host bus and an internal system bus within a graphics controller is disclosed. The queue comprises a First In First Out (FIFO) memory having independent clocks for reading and writing. The queue accommodates address information, data, command information, byte enable information, decode information, and a tag. The tag is a 2 bit field used to identify the queued entries as address, last data, and burst data. In a preferred embodiment, single transactions are written to the queue with no wait states. In the case of an address entry, the address associated with the transaction is stored in the queue along with the command and decode information. A tag is also included that identifies the entry as an address. In the case of a final data entry, the data is stored in the next entry along with the byte enable information and a tag to indicate it is the last data of the transaction. In the case of a burst, the address entry is followed by multiple data entries that are each tagged as burst data. The final data entry of the burst will be tagged as the last data of the transaction in the same way as the data of a single transaction.

Transaction queue in a graphics controller chip

A method and apparatus to stretch video images in a graphics controller chip of a computer system. The graphics controller chip fetches four pixel data comprising two pixel data each from a first scan line and a second scan line of a source video image, and generates a set of additional pixels in a rectangular area defined by the four pixels. The graphics controller chip stores the pixels of rectangular portions in a display memory, and displays the pixel data of the stretched video image in a scan line order.

Method and apparatus for minimizing number of pixel data fetches

Growing community of inventors

Lynnwood, WA, United States of America

Karl Scott Mills