Telefonaktiebolaget Lm Ericsson (publ)

Karl S Buhrgard

Hao Jiang

Tord L Haulin

Mats L Lindblom

Johan U Tingsborg

The present invention relates to a multiplexing/demultiplexing unit constructed as an integrated circuit and as a block on a sub-surface of a silicon surface, such as a digital Bi-CMOS circuit and utilizing a CMOS section laid on said circuit, wherein a first sub-surface of a silicon surface carries a first array (41') of signal input and output circuits, and a second sub-surface carries a second array (41') of input and output circuits. A region (50) is located on the silicon surface between the first and the second sub-surfaces or located in some corresponding manner and is intended to carry control logic (51), memory stores (52), buffer circuits (53), synchronizing circuit arrangement (54) and the requisite conductors and functions to process signals, store signals and transmit the processed signals on selected output circuits both when multiplexing and demultiplexing signals.

Multiplexing/demultiplexing unit arranged on a multi-surface integrated

A signal receiving and a signal transmitting unit converts an information carrying signal received at a first transmission rate to an information carrying signal transmitted at a second transmission rate that differs from the first transmission rate. Several inputs and outputs are available, each input structured for a transmission rate that is different from the transmission rates of remaining inputs, and each output structured for a transmission rate that is different from the transmission rates of remaining outputs. One signal receiving input can be connected to one signal transmitting output depending on signals occurring on one or more control conductors, wherein a selected control conductor and/or selected signal information selects and initiates a conversion mode having a selected conversion index.

Signal receiving and transmitting unit for converting a transmission

A synchronizing circuit arrangement included in a multiplexing/demultiplexing unit receives a bit stream coordinated to a data packet. The bit positions and values within a predetermined part of a consecutive bit sequence of each transmitted data packet are constantly selected so that a predetermined check calculation will give a predetermined value (for instance, '0'). A consecutive bit sequence corresponding to the predetermined part of a consecutive bit sequence and belonging to respective received data packets is evaluated in order to establish the extent to which the check calculation gives the predetermined value. When agreement is found, it is assumed that the boundary between two closely adjacent data packets is established via the bit sequence of the predetermined part of a consecutive bit sequence. Each incoming bit stream is synchronized through the medium of a control block or control logic by inserting a time delay corresponding to synchronism into a series-parallel converter for respective bit streams. The synchronized, parallel-format bit streams can be delivered via the control block or control logic to a memory which delivers the bit stream to the outgoing connection via buffer circuits and a parallel-series converter.

Synchronizing circuit arrangement

A signal processing arrangement processes an incoming bit position carrying signal and produces an outgoing bit position carrying signal. The arrangement comprises a signal processing unit for processing the incoming bit position carrying signal to produce an outgoing bit position carrying signal. The incoming bit position carrying signal is time-controlled in relation to a first clock signal. The outgoing bit position carrying signal is time-controlled in relation to the first clock signal. A second clock signal having the same frequency as the first clock signal is used for processing the incoming bit position carrying signal into a processed incoming bit position carrying signal within the signal processing unit. A synchronizing unit synchronizes processing for the signal processing unit by changing the time-relationship of clock pulses of the second clock signal to synchronize with the incoming bit position carrying signal. Buffer circuits store the processed incoming bit position carrying signal. The timing of the processed incoming bit position carrying signal can be changed to synchronize with clock pulses of the first clock signal before the processed incoming bit position carrying signal is output as the outgoing bit position carrying signal.

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Stockholm, Sweden

Karl S Buhrgard