Fairchild Semiconductor Corporation

Karl Rapp

Bob Roohparvar

K Z Mahouti

Etan Shacham

Ethan A Crain

Kevin Z Mahouti

A low read current, low power consumption sense amplifier well suited for low frequency RFID systems is disclosed. An MOS transistor receives the read current from a memory cell, typically an EEPROM, and a current mirror is formed by a parallel MOS transistor. The mirror current is integrated on a capacitor after the charge on the capacitor is cleared via a reset pulse. A time period is defined during which the voltage on the capacitor is compared to a second voltage. The second voltage is formed from a reference voltage or from dummy cells, in either case the reference voltage is at about the logic boundary between a one and zero stored in a memory cell. A comparator, with or without input hysteresis, receives the voltage on the capacitor and a second voltage and within the time period, the output state of the comparator indicates the binary contents of the memory cell.

Current integrating sense amplifier for memory modules in RFID

A charge pump system, including a charge pump and associated distributed clock generation circuitry, is provided for generating high voltages from a low initial voltage in applications such as erasing and programming electrically erasable programmable read only memory (EEPROM) arrays. The charge pump system uses a power supply voltage and a clock and includes a first phase bootstrapping circuit, an inverter, and a second phase bootstrapping circuit, and a two-stage charge pump. The two phase bootstrapping circuits are both responsive to the clock and use a distributed bootstrapping scheme to provide first and second phase clock signals with fixed multiples of the power supply voltage in order to overcome increased effective transistor threshold voltages, increase efficiency, and allow for charge boosting in a limited number of stages. The inverter is connected to the second phase bootstrapping circuit, causing the second phase clock signal to be opposite in phase from the first clock signal. The two-stage charge pump is responsive to the power supply voltage and the first and second phase clocks and uses native transistors that have lower threshold voltages. A high voltage is produced from the two-stage charge pump by alternately adding charge to the power supply voltage in each cycle of the first and second phase clock signals.

Low voltage charge pump employing distributed charge boosting

A charge pump system and associated variable-amplitude clock generation circuitry are provided for generating high voltages from a low initial voltage in applications such as erasing and programming electrically erasable programmable read only memory (EEPROM) arrays. The charge pump system uses a power supply voltage and a clock and includes a first phase bootstrapping circuit, an inverter, and a second phase bootstrapping circuit, and charge pump circuitry. The two phase bootstrapping circuits are both responsive to the clock and provide first and second phase clock signals. The inverter is connected to the second phase bootstrapping circuit, causing the second phase clock signal to be opposite in phase from the first clock signal. The charge pump circuitry is responsive to the power supply voltage and the first and second phase clocks and uses native transistors that have lower threshold voltages. A high voltage is produced from the charge pump circuitry by alternately adding charge to the power supply voltage in each cycle of the first and second phase clock signals. The first and second phase clock signals increase in voltage as the voltage level in the charge pump increases in order to overcome increased effective transistor threshold voltages.

Low voltage charge employing optimized clock amplitudes

A charge pump system includes a charge pumping circuit for outputting a high voltage V at a node. An oscillator circuit, coupled to the charge pumping circuit, drives the charge pumping circuit with at least one clock signal. A current source generates a pulldown current. A voltage divider circuit is coupled between the node and the current source. The voltage divider circuit cooperates with the current source to form a feedback loop for controlling the oscillator circuit to run at variable, optimum frequency for controlling the rate-of-rise and the amplitude of the high voltage V while minimizing power-supply current drain.

Growing community of inventors

Los Gatos, CA, United States of America

Karl Rapp