Koninklijke Philips Corporation N.v.

Philips Electronics North America Corporation

North American Philips Corporation

U.S. Philips Corporation

Nxp B.v.

Bell Telephone Laboratories

Karl R Wittig

Michael Bakhmutsky

Mikhail Tsinberg

Samir N Hulyalkar

Alan P Cavallerano

Gene Turkenich

Dagnachew Birru

Kiran Srinivas Challapali

Javier Del Prado Pavon

Richard Chen

Chun-Ting Chou

Carlo Basile

Alan Peter Cavallerano

Sai Shankar Nandagopalan

Ruediger Schmitt

Richard C Shen

Geoffrey Francis Burns

Alan M Gordon

Gerry C Balzer

Hari Thirumoorthy

Olu Akiwumi-Assani

Michael W Leibowitz

To maximize power saving performance without compromising on the QoS requirement of an application stream, a method and wireless network device generates a subset of a periodic service interval can be used for medium time allocation and data and information can be transmitted in contiguous medium time allocated this way. This selection of a period of time below service capacity allows multiple applications access the medium and for the selection of contiguous medium time during which data transmission can occur.

Quality of service provisioning using periodic channel time allocation

A method and apparatus for efficiently generating complex sinusoids of a desired frequency by multiplying a phasor by a predetermined value once every sampling interval, and using the highest order bits within the phasor to identify if the phasor is at an integer multiple 45 degrees and substituting components in the phasor if it is determined that the phasor is an integer multiple of 45 degrees. If the phasor is not identified as being an integer multiple of 45 degrees then an error factor for both the real and imaginary components is determined and the real and imaginary components are corrected by removing the error factor.

Free-running numerically-controlled oscillator using complex multiplication with compensation for amplitude variation due to cumulative round-off errors

The present invention is directed to a reconfigurable finite impulse response (FIR) filter that processes data tap values with canonical sign digit (CSD) coefficients. The FIR filter according to the present invention includes a shift group associated with at least one of the data tap values and at least one of the CSD coefficients. Each shift group includes a plurality of parallel paths. Each parallel path shifts the data tap value according to a bit pair of the coefficient to produce a weighted product. An adder is also included that combines the weighted products from each of the shift groups.

Reconfigurable FIR filter using CSD coefficient representation

A method and apparatus for determining an image noise estimate value in a digital video processing system using only a single video image. In the method and apparatus, SAD values in the video image are calculated. For each SAD value, a determination is made as to whether the SAD value falls within one or more of a plurality of predetermined SAD value ranges, each of which corresponds to a prospective image noise estimate value. The determination is made concurrently for all of the predetermined SAD value ranges. For each one of the SAD value ranges, the number of SAD values that fall within that predetermined SAD value range is counted. The prospective image noise estimate having a count value that meets predetermined criteria is then selected as the image noise estimate value in the digital video processing system.

Method and apparatus for fast robust estimation of image noise in a video processing system

For use in a receiver capable of decoding trellis encoded signals of the type comprising a trellis decoder and a decision feedback equalizer coupled to each path memory output of said trellis decoder, wherein said decision feedback equalizer is capable of obtaining symbol values from each path memory output of said trellis decoder for use as estimates in channel equalization, an apparatus and method is disclosed for reconstructing symbol values from trace back path information stored within said trellis decoder. The apparatus and method of the present invention reconstructs a symbol stream from the trellis decoder using data signal selection circuitry to obtain bit values that represent the reconstructed symbols. In one embodiment of the present invention, each of a plurality of multiplexers selects one of four symbol value inputs to send to a first adaptive filter tap cell in a set of twelve adaptive filter tap cells. The four symbol values represent (1) a symbol at trellis point &ldquo;t&rdquo;, and (2) a symbol at trellis point &ldquo;t&minus;12&rdquo;, and (3) a symbol having the value &ldquo;plus five&rdquo;, and (4) a symbol having the value &ldquo;minus five.&rdquo;

Generation of decision feedback equalizer data using trellis decoder traceback output in an ATSC HDTV receiver

There is disclosed a system and method for recovering a recurring data segment synchronization pattern in the presence of an arbitrary phase rotation of a pilot carrier by detecting and compensating for the amount of the phase rotation. The system comprises a first synchronization pattern detector capable of receiving a real component of a complex signal and detecting a data segment synchronization pattern on the real component, and a second synchronization pattern detector capable of receiving an imaginary component of a complex signal and detecting a data segment synchronization pattern on the imaginary component. There is also disclosed a method for compensating a pilot carrier phase rotation comprising the steps of determining the angle of pilot carrier phase rotation present in a complex signal and rotating the pilot carrier signal through the same angle in the opposite direction. Methods are also disclosed for compensating signal gain in a complex signal in which pilot carrier phase rotation has occurred.

System and method of synchronization recovery in the presence of pilot carrier phase rotation for an ATSC-HDTV receiver

A digital filter includes a plurality of filter cells, each of which includes circuitry to determine a coefficient for the filter cell, to adjust the coefficient in accordance with a gain that is used by each of the plurality of filter cells, and to multiply input data by the adjusted coefficient in order to generate a filter cell output. An adder circuit generates a filter output by adding filter cell outputs from each of the plurality of filter cells, and an inverse gain circuit adjusts the filter output in accordance with an inverse of the gain used to adjust the coefficients of the plurality of filter cells.

System for varying the dynamic range of coefficients in a digital filter

A method for motion coding an uncompressed digital video data stream such as an MPEG-2 digital video data stream. The method includes the steps of comparing pixels of a first pixel array in a picture currently being coded with pixels of a plurality of second pixel arrays in at least one reference picture and concurrently performing motion estimation for each of a plurality of different prediction modes in order to determine which of the prediction modes is an optimum prediction mode determining which of the second pixel arrays constitutes a best match with respect to the first pixel array for the optimum prediction mode, and, generating a motion vector for the first pixel array in response to the determining step. The method is implemented in a device such as a motion estimation search system of a digital video encoder. In one embodiment, the method and device are capable of concurrently determining performing motion estimation in each of the six different possible prediction modes specified by the MPEG-2 standard.

Method of concurrent multiple-mode motion estimation for digital video

A system for interpolating half-pels from a pixel array stores pixel data for each pixel in one of a plurality of different memory areas based on a location of the pixel within the pixel array, and determines a specific address in each one of the plurality of memory areas based on a target pixel in the pixel array. The system determines each specific address based on a location of the target pixel in the pixel array. The system also reads, from each the plurality of memory areas, pixel data from determined specific addresses and determines a value of at least one half-pel for the target pixel based on the read pixel data.

Pixel data storage system for use in half-pel interpolation

In the standard format now adapted by FCC for a digital HDTV signal, the video data symbols are interleaved and trellis encoded in accordance with a 4-state trellis code and the interleaving is of sequences of every 12 successive symbols. At the receiver the trellis decoder is therefore projected to consist of 12 respective decoder stages for the 12 interleaved sequences, each decoder stage having a branch metric calculator unit (BMC), an add-compare-select (ACS) unit and a path memory unit (PMU). The present invention separates the path memory requirements for the 12 interleaved sequences from the requisite BMC and ACS functions, so that the latter two units can provide those functions for all of the 12 interleaved sequences. A single extended PMU provides for storage of pointers to possible predecessor states of the trellis code corresponding to a present state thereof, going back to a predetermined number (such as 16) of sequentially preceding received symbol values. The PMU also provides, in each of the storage stages, sequential storage elements corresponding to the sequential interleaved symbol values. This makes it possible for the PMU to be realized as a single integrated RAM by appropriate grouping of the trellis code states. Also, the ACS function is performed by two separate ACS units for two mutually independent groups of trellis code states.

Decoder for trellis encoded interleaved data stream and HDTV receiver

A digital filter has a filter cell for generating processed data. The digital filter cell includes plurality of coefficient registers which are arranged to circulate a plurality of coefficient values that correspond to a plurality of coefficients such that each of the plurality of coefficients is output once during a predetermined period. One or more data registers are arranged to circulate a data value for a time which is at least as long as the predetermined period such that the data value is output each time that a different one of the plurality of coefficients is output. A circuit receives each output data value and each output coefficient and generates processed data by processing each output data value with each output coefficient.

System for sharing resources in a digital filter

An error computation processor for use in a Reed Solomon decoder for computing the error locations and magnitudes of a large data block having a maximum of t errors over a desired Galois field. The processor can compute the error-locator polynomial, the error-evaluator polynomial, and the values of the errors whose location was determined to be in error with only two polynomial storage registers, two element storage registers, one multiplier for performing selected multiplication and division, one adder for performing selected addition and subtraction, one error locator stack, one error value stack, and a syndrome register for storing the syndromes of the large data block.

Hardware-optimized reed-solomon decoder for large data blocks

An MPEG decoder includes a dual-speed variable length decoder (VLD) in which a code length determining portion in a feedback loop of the VLD, which loop also includes a barrel shifter and an adder-accumulator, is formed of two length tables, a high speed first length table for producing a code length determination within one clock cycle for the non-DC discrete cosine transform (DCT) coefficients and a slower speed second code length table which produces a code length determination generally in two or more clock cycles. A DCT coefficient run length decoder receives DCT coefficient codewords from the VLD consisting of level/run pairs and is configured for decoding any level/run pair in one clock cycle. By concentrating decoding speed on the variable length DCT coefficients which constitute much of the data in an MPEG data stream, sufficient decoding speed is obtained to handle MPEG-2 video as proposed for high definition television (HDTV).

Growing community of inventors

New York, NY, United States of America

Karl R Wittig