International Business Machines Corporation

Kabushiki Kaisha Toshiba

Karl R Hense

Paul Wingshing Chung

Jerome D Harr

John E Gersbach

Thomas W Collins

Shoichi Shimizu

Bac V Pham

Douglas W Gorgen

Robert W Donner

Kim Y Nguyen

Pete Granata

Switched pull down (SPD) ECL circuits have a switching circuit within the pull down portion of the output stage, so that a large portion of the total pull down current is switched to the negative going output node, and so that a small portion of the total pull down current is switched to the positive going output node. The negative going output node has a larger that normal ECL pull down current attached to it. The larger pull down current on the negative going node discharges the output capacitor in a shorter period of time. The shorter discharge time of negative going output results in a shorter fall delay time. Two smaller current sources are connected to each of the two differential ECL outputs to insure that both pull up transistors are forward biased so as to provide an adequate noise margin and insure correct circuit operation. Forward biasing the pull up transistors with a minimum acceptable amount of bias current at the emitters of the output pull up transistors provides proper immunity to noise.

Switched pull down emitter coupled logic circuits

An analog receiver circuit suitable for use with a flash analog-to-digital converter is described. A first stage of the receiver acts essentially as a voltage follower, receiving the centertap voltage of a flash A/D converter resistor ladder, and maintaining an internal reference voltage substantially equal to the centertap voltage over time. A second stage of the analog receiver acts as centering means, receiving an analog signal and centering it with respect to the internal reference voltage provided by the first stage. The receiver is thus able to provide an analog signal to the flash A/D converter which is dynamically centered with respect to the converter's operating voltage, thereby reducing DC offset. Moreover, introducing the analog signal at the second stage minimizes the bandwidth-limiting elements between this input signal and the DC-centered output signal. Thus DC offset is further reduced and operating frequencies of 500 MTz or greater are possible.

DC centering analog receiver for flash A/D converter

A high performance, low power analog to digital converter is designed in BIFET technology utilizing the high gain, high performance of a bipolar comparator and the low power of a CMOS latch and CMOS encoding logic circuits. Using a FET dynamic latch, metastability is avoided, significantly reducing soft error rate.

BiCMOS analog-to-digital converter with minimized metastability

A recording channel for a disk file including analog circuits implemented in integrated circuits whose frequency dependent parameters are controllable in response to the value of a control signal supplied to the circuit, as determined by a digital signal. In the preferred embodiment, the control signal to each analog circuit is from a digital to analog converter that is supplied with a digital signal from a register that is addressable and settable from a programmed microcontroller. Certain registers are able to be incremented or decremented by separate clock pulses and function as counters that are controlled by a signal in a feedback path separate from the microcontroller. Components external to the integrated circuits are, therefore, avoided while still maintaining the ability to adjust the analog read circuits to be responsive to data rates of different frequencies.

Recording channel with signal controlled integrated analog circuits

Operating circuitry for linear charge launching, non-destructive weighting and non-destructive charge sensing for Charge Coupled Devices (CCD) employs electronic integrating circuitry at the input and output node terminals of the CCD. Feedback circuitry within the integrating circuitry aids in linearizing the signals, in eliminating the non-linear capacitance effect of the depletion regions, and in freeing the design from device parameter variations such as electrode area and absolute values of threshold potential and thickness of insulating layer. The circuitry is adaptable to most conventional CCD and is readily made up of conventional resistance and capacitance elements, of conventional comparing circuits such as differential amplifying or signal repeating circuits, and of conventional summing circuitry.

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Los Altos, CA, United States of America

Karl R Hense