International Business Machines Corporation

Kabushiki Kaisha Toshiba

Siemens Aktiengesellschaft

Other

Siemens Aktiengesell Schaft

Karl Paul Muller

Klaus B Roithner

Bernhard Poschenrieder

Theodore Gerard Van Kessel

Wesley Charles Natzle

Katsuya Okumura

Venkatachalam C Jaiprakash

Richard L Kleinhenz

Hans-Joerg Timme

Isahiro Hasegawa

Christopher J Gould

Toru Watanabe

Masakatsu Tuschiaki

Bernhard L Poschenriedes

The present invention is an apparatus for distributing reactant gases across the substrate mounted in a reaction chamber. The apparatus is capable of being utilized in both vapor deposition and etching processes. The apparatus substantially compensates for the problem of non-uniformity of vapor deposition and etching at the edges of the wafers caused by gas depletion. A gas distribution plate having a plurality of apertures extending therethrough is attached to an interior surface of the reaction chamber. At least one vacuum sealed partition is disposed between a surface of the gas distribution plate and the interior surface of the chamber. The partition separates the space between the plate and reaction chamber into gas distribution zones. A gas inlet is connected to each gas distribution zone. Each gas inlet line has at least one mass flow controller which regulates the flow of gas to each gas distribution zone. The mass flow controllers are utilized to ensure a uniform rate of chemical vapor deposition or etching across the surface of the substrate.

Distribution plate for a reaction chamber with multiple gas inlets and separate mass flow control loops

Misalignment between two masking steps used in the manufacture of semiconductive devices in a wafer is determined by having a special alignment pattern on each of two masks used in the process and forming images of the masks on the semiconductor devices with the images of the alignment patterns being superimposed over one another to form a Moire pattern. The Moire pattern is compared with other Moire patterns known to correspond to particular amounts of misalignment of the masks to see if it corresponds to an acceptable alignment.

Overlay measurement technique using moire patterns

Isotropic deposition of a selectively etchable material in an opening in a body of material followed by isotropic deposition of an etch resistant material forms a mask for anisotropic etching of the selectively etchable material at potentially sub-lithographic dimensions to form potentially sub-lithographic features within a trench. This process can be exploited to form a folded trench capacitor in which a trench is formed with one or more upstanding and possibly hollow features therein; effectively multiplying the surface area and or allowing reduced trench depth for a given charge storage capacity or a combination thereof. Further surface treatments such as deposition of hemispherical grain silicon can be used to further enhance the effective area of the trench. Isolation structures of sub-lithographic dimensions can also be formed by depositing appropriate materials within the trenches formed in accordance with the mask.

Folded trench and RIE/deposition process for high-value capacitors

A method for allowing the removal of a TEOS etch mask layer utilizing an anisotropic technique such as reactive ion etching. The use of the anisotropic technique results in substantially less undercutting of the pad oxide layer than wet chemical etching techniques. One embodiment of the invention involves forming a polysilicon etch stop layer under the pad TEOS layer.

Pad stack with a poly SI etch stop for TEOS mask removal with RIE

The processing of a semiconductor body front side surface can be monitored in-situ, and thickness data for a body can be obtained ex-situ, by directing an infrared beam at the back side surface of the body. The light is reflected from front and back sides of a body portion to form primary and secondary reflections which are detected. An interference signal representative of interference fringes of the primary and secondary reflections is generated, and thickness data for the body or a body portion is calculated from the interference signal. In-situ monitoring of processes such as mechanical-chemical polishing, chemical vapor deposition, and plasma or reactive ion etching is achieved by providing a light passageway through a semiconductor body support such as a chuck or electrode, e.g., a cathode. In this manner, the process monitoring does not hinder, and is not hindered by, the processing steps and equipment.

Process monitoring and thickness measurement from the back side of a

A temperature control apparatus for single wafer etching tools comprising a cathode electrode, an isolation layer, and chuck means, respectfully, which are vertically stacked to support a wafer to be etched. A layer of thermoelectric elements is disposed between the isolation layer and the chuck means. The layer of thermoelectric elements comprises a center area closed loop of connected Peltier elements and an outer area closed loop of connected Peltier elements. The center area closed loop is coupled to a power source and is arranged to correspond to the center area of the wafer. The outer area closed loop is coupled to a power source and is arranged to correspond to the outer area of the wafer. Accordingly, the temperatures associated with each of the specific areas of the wafer are individually controlled by one of the closed loops.

In-situ wafer temperature control apparatus for single wafer tools

Folded trench and rie/deposition process for high-value capacitors

In a method of etch profile shaping through wafer temperature control during an etch process wherein deposition of a passivation film is temperature dependent, a gap between a semiconductor wafer to be etched and a cathode is pressurized at a first pressure, and the pressure in the gap is changed to a second pressure at a predetermined time during the etch process, thereby altering heat transfer from the semiconductor wafer to the cathode. The temperature of the wafer is adjusted one or more times during an etching process to control profile shaping of deep trenches, contact holes and shapes for mask opening shaping during the etch process.

Etch profile shaping through wafer temperature control

A capacitance storage trench for a DRAM cell includes a trench having at least one sidewall, a bottom wall and a plurality of rods extending away from the bottom wall. The at least one sidewall, the bottom wall and the rods are coated with a capacitive dielectric layer. A layer of semiconductive material is disposed over the dielectric layer. The plurality of rods expand the overall surface area of the trench and thus, provide a significant increase in capacitance storage of the storage trench. The capacitance storage trench is formed in a method which includes the steps of forming a plurality of buried oxygen precipitates in a selected region of a substrate and using the oxygen precipitates as micromasks during a conventional trench etch process.

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Wappingers Falls, NY, United States of America

Karl Paul Muller